91276c0fa4
BAST is the one machine that theoretically supports unmodified ISA drivers for hardware on its PC/104 connector, using a custom version of the inb()/outb() and inw()/outw() macros. This is incompatible with the generic version used in asm/io.h, and can't easily be used in a multiplatform kernel. Removing the special case for 16-bit I/O port access on BAST gets us closer to multiplatform, at the expense of any PC/104 users with 16-bit cards having to either use an older kernel or modify their ISA drivers to manually ioremap() the area and use readw()/write() in place of inw()/outw(). Either way is probably ok, given that there is a recurring discussion about dropping s3c24xx altogether, and many traditional ISA drivers are already gone. Machines other than BAST already have no support for ISA drivers, though a couple of them do map one of the external chip-selects into the ISA port range, using the same address for 8-bit and 16-bit I/O. It is unlikely that anything actually uses this mapping, but it's also easy to keep this working by mapping it to the normal platform-independent PCI I/O base that is otherwise unused on s3c24xx. The mach/map-base.h file is no longer referenced in global headers and can be moved into the platform directory. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
116 lines
2.5 KiB
C
116 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2003-2004 Simtec Electronics
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// Ben Dooks <ben@simtec.co.uk>
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// http://armlinux.simtec.co.uk/
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//
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// S3C24XX - IRQ PM code
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/syscore_ops.h>
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#include <linux/io.h>
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#include "cpu.h"
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#include "pm.h"
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#include "map-base.h"
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#include "map-s3c.h"
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#include "regs-irq.h"
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#include "regs-gpio.h"
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#include "pm-core.h"
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#include <asm/irq.h>
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int s3c_irq_wake(struct irq_data *data, unsigned int state)
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{
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unsigned long irqbit = 1 << data->hwirq;
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if (!(s3c_irqwake_intallow & irqbit))
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return -ENOENT;
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pr_info("wake %s for hwirq %lu\n",
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state ? "enabled" : "disabled", data->hwirq);
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if (!state)
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s3c_irqwake_intmask |= irqbit;
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else
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s3c_irqwake_intmask &= ~irqbit;
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return 0;
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}
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static struct sleep_save irq_save[] = {
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SAVE_ITEM(S3C2410_INTMSK),
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SAVE_ITEM(S3C2410_INTSUBMSK),
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};
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/* the extint values move between the s3c2410/s3c2440 and the s3c2412
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* so we use an array to hold them, and to calculate the address of
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* the register at run-time
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*/
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static unsigned long save_extint[3];
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static unsigned long save_eintflt[4];
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static unsigned long save_eintmask;
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static int s3c24xx_irq_suspend(void)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(save_extint); i++)
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save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
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for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
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save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
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s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
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save_eintmask = __raw_readl(S3C24XX_EINTMASK);
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return 0;
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}
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static void s3c24xx_irq_resume(void)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(save_extint); i++)
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__raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
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for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
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__raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
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s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
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__raw_writel(save_eintmask, S3C24XX_EINTMASK);
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}
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struct syscore_ops s3c24xx_irq_syscore_ops = {
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.suspend = s3c24xx_irq_suspend,
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.resume = s3c24xx_irq_resume,
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};
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#ifdef CONFIG_CPU_S3C2416
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static struct sleep_save s3c2416_irq_save[] = {
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SAVE_ITEM(S3C2416_INTMSK2),
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};
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static int s3c2416_irq_suspend(void)
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{
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s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
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return 0;
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}
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static void s3c2416_irq_resume(void)
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{
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s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
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}
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struct syscore_ops s3c2416_irq_syscore_ops = {
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.suspend = s3c2416_irq_suspend,
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.resume = s3c2416_irq_resume,
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};
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#endif
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