716129d3b7
Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230209143702.44408-3-hal.feng@starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
138 lines
3.1 KiB
C
138 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
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#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
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/* sys_iomux pins */
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#define PAD_GPIO0 0
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#define PAD_GPIO1 1
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#define PAD_GPIO2 2
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#define PAD_GPIO3 3
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#define PAD_GPIO4 4
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#define PAD_GPIO5 5
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#define PAD_GPIO6 6
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#define PAD_GPIO7 7
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#define PAD_GPIO8 8
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#define PAD_GPIO9 9
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#define PAD_GPIO10 10
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#define PAD_GPIO11 11
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#define PAD_GPIO12 12
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#define PAD_GPIO13 13
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#define PAD_GPIO14 14
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#define PAD_GPIO15 15
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#define PAD_GPIO16 16
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#define PAD_GPIO17 17
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#define PAD_GPIO18 18
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#define PAD_GPIO19 19
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#define PAD_GPIO20 20
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#define PAD_GPIO21 21
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#define PAD_GPIO22 22
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#define PAD_GPIO23 23
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#define PAD_GPIO24 24
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#define PAD_GPIO25 25
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#define PAD_GPIO26 26
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#define PAD_GPIO27 27
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#define PAD_GPIO28 28
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#define PAD_GPIO29 29
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#define PAD_GPIO30 30
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#define PAD_GPIO31 31
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#define PAD_GPIO32 32
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#define PAD_GPIO33 33
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#define PAD_GPIO34 34
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#define PAD_GPIO35 35
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#define PAD_GPIO36 36
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#define PAD_GPIO37 37
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#define PAD_GPIO38 38
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#define PAD_GPIO39 39
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#define PAD_GPIO40 40
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#define PAD_GPIO41 41
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#define PAD_GPIO42 42
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#define PAD_GPIO43 43
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#define PAD_GPIO44 44
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#define PAD_GPIO45 45
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#define PAD_GPIO46 46
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#define PAD_GPIO47 47
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#define PAD_GPIO48 48
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#define PAD_GPIO49 49
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#define PAD_GPIO50 50
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#define PAD_GPIO51 51
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#define PAD_GPIO52 52
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#define PAD_GPIO53 53
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#define PAD_GPIO54 54
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#define PAD_GPIO55 55
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#define PAD_GPIO56 56
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#define PAD_GPIO57 57
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#define PAD_GPIO58 58
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#define PAD_GPIO59 59
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#define PAD_GPIO60 60
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#define PAD_GPIO61 61
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#define PAD_GPIO62 62
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#define PAD_GPIO63 63
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#define PAD_SD0_CLK 64
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#define PAD_SD0_CMD 65
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#define PAD_SD0_DATA0 66
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#define PAD_SD0_DATA1 67
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#define PAD_SD0_DATA2 68
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#define PAD_SD0_DATA3 69
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#define PAD_SD0_DATA4 70
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#define PAD_SD0_DATA5 71
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#define PAD_SD0_DATA6 72
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#define PAD_SD0_DATA7 73
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#define PAD_SD0_STRB 74
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#define PAD_GMAC1_MDC 75
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#define PAD_GMAC1_MDIO 76
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#define PAD_GMAC1_RXD0 77
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#define PAD_GMAC1_RXD1 78
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#define PAD_GMAC1_RXD2 79
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#define PAD_GMAC1_RXD3 80
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#define PAD_GMAC1_RXDV 81
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#define PAD_GMAC1_RXC 82
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#define PAD_GMAC1_TXD0 83
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#define PAD_GMAC1_TXD1 84
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#define PAD_GMAC1_TXD2 85
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#define PAD_GMAC1_TXD3 86
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#define PAD_GMAC1_TXEN 87
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#define PAD_GMAC1_TXC 88
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#define PAD_QSPI_SCLK 89
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#define PAD_QSPI_CS0 90
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#define PAD_QSPI_DATA0 91
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#define PAD_QSPI_DATA1 92
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#define PAD_QSPI_DATA2 93
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#define PAD_QSPI_DATA3 94
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/* aon_iomux pins */
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#define PAD_TESTEN 0
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#define PAD_RGPIO0 1
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#define PAD_RGPIO1 2
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#define PAD_RGPIO2 3
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#define PAD_RGPIO3 4
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#define PAD_RSTN 5
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#define PAD_GMAC0_MDC 6
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#define PAD_GMAC0_MDIO 7
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#define PAD_GMAC0_RXD0 8
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#define PAD_GMAC0_RXD1 9
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#define PAD_GMAC0_RXD2 10
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#define PAD_GMAC0_RXD3 11
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#define PAD_GMAC0_RXDV 12
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#define PAD_GMAC0_RXC 13
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#define PAD_GMAC0_TXD0 14
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#define PAD_GMAC0_TXD1 15
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#define PAD_GMAC0_TXD2 16
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#define PAD_GMAC0_TXD3 17
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#define PAD_GMAC0_TXEN 18
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#define PAD_GMAC0_TXC 19
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#define GPOUT_LOW 0
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#define GPOUT_HIGH 1
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#define GPOEN_ENABLE 0
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#define GPOEN_DISABLE 1
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#define GPI_NONE 255
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#endif
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