e47616df00
This change adds support to configure dspp blocks in the dpu driver. Macro description of the changes coming in this patch. 1) Add dspp definitions in the hw catalog. 2) Add capability to reserve dspp blocks in the display data path. 3) Attach the reserved block to the encoder. Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Tested-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
92 lines
2.8 KiB
C
92 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef __DPU_RM_H__
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#define __DPU_RM_H__
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#include <linux/list.h>
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#include "msm_kms.h"
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#include "dpu_hw_top.h"
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struct dpu_global_state;
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/**
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* struct dpu_rm - DPU dynamic hardware resource manager
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* @pingpong_blks: array of pingpong hardware resources
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* @mixer_blks: array of layer mixer hardware resources
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* @ctl_blks: array of ctl hardware resources
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* @intf_blks: array of intf hardware resources
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* @dspp_blks: array of dspp hardware resources
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* @lm_max_width: cached layer mixer maximum width
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* @rm_lock: resource manager mutex
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*/
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struct dpu_rm {
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struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
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struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
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struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
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struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
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struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
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uint32_t lm_max_width;
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};
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/**
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* dpu_rm_init - Read hardware catalog and create reservation tracking objects
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* for all HW blocks.
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* @rm: DPU Resource Manager handle
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* @cat: Pointer to hardware catalog
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* @mmio: mapped register io address of MDP
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* @Return: 0 on Success otherwise -ERROR
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*/
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int dpu_rm_init(struct dpu_rm *rm,
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struct dpu_mdss_cfg *cat,
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void __iomem *mmio);
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/**
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* dpu_rm_destroy - Free all memory allocated by dpu_rm_init
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* @rm: DPU Resource Manager handle
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* @Return: 0 on Success otherwise -ERROR
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*/
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int dpu_rm_destroy(struct dpu_rm *rm);
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/**
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* dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze
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* the use connections and user requirements, specified through related
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* topology control properties, and reserve hardware blocks to that
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* display chain.
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* HW blocks can then be accessed through dpu_rm_get_* functions.
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* HW Reservations should be released via dpu_rm_release_hw.
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* @rm: DPU Resource Manager handle
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* @drm_enc: DRM Encoder handle
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* @crtc_state: Proposed Atomic DRM CRTC State handle
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* @topology: Pointer to topology info for the display
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* @Return: 0 on Success otherwise -ERROR
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*/
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int dpu_rm_reserve(struct dpu_rm *rm,
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struct dpu_global_state *global_state,
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struct drm_encoder *drm_enc,
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struct drm_crtc_state *crtc_state,
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struct msm_display_topology topology);
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/**
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* dpu_rm_reserve - Given the encoder for the display chain, release any
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* HW blocks previously reserved for that use case.
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* @rm: DPU Resource Manager handle
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* @enc: DRM Encoder handle
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* @Return: 0 on Success otherwise -ERROR
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*/
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void dpu_rm_release(struct dpu_global_state *global_state,
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struct drm_encoder *enc);
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/**
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* Get hw resources of the given type that are assigned to this encoder.
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*/
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int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
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struct dpu_global_state *global_state, uint32_t enc_id,
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enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
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#endif /* __DPU_RM_H__ */
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