5c541b884c
Add new Tegra 114 SoC support. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
132 lines
2.9 KiB
C
132 lines
2.9 KiB
C
/*
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* arch/arm/mach-tegra/common.c
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/of_irq.h>
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#include <linux/clk/tegra.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <mach/powergate.h>
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#include "board.h"
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#include "common.h"
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#include "fuse.h"
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#include "iomap.h"
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#include "pmc.h"
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#include "apbio.h"
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#include "sleep.h"
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#include "pm.h"
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#include "reset.h"
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/*
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* Storage for debug-macro.S's state.
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*
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* This must be in .data not .bss so that it gets initialized each time the
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* kernel is loaded. The data is declared here rather than debug-macro.S so
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* that multiple inclusions of debug-macro.S point at the same data.
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*/
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u32 tegra_uart_config[4] = {
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/* Debug UART initialization required */
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1,
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/* Debug UART physical address */
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0,
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/* Debug UART virtual address */
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0,
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/* Scratch space for debug macro */
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0,
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};
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#ifdef CONFIG_OF
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static const struct of_device_id tegra_dt_irq_match[] __initconst = {
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{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init },
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{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
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{ }
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};
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void __init tegra_dt_init_irq(void)
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{
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tegra_clocks_init();
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tegra_init_irq();
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of_irq_init(tegra_dt_irq_match);
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}
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#endif
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void tegra_assert_system_reset(char mode, const char *cmd)
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{
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void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
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u32 reg;
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reg = readl_relaxed(reset);
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reg |= 0x10;
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writel_relaxed(reg, reset);
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}
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static void __init tegra_init_cache(void)
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{
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#ifdef CONFIG_CACHE_L2X0
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int ret;
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void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
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u32 aux_ctrl, cache_type;
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cache_type = readl(p + L2X0_CACHE_TYPE);
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aux_ctrl = (cache_type & 0x700) << (17-8);
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aux_ctrl |= 0x7C400001;
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ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
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if (!ret)
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l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
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#endif
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}
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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void __init tegra20_init_early(void)
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{
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tegra_cpu_reset_handler_init();
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tegra_apb_io_init();
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tegra_init_fuse();
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tegra_init_cache();
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tegra_pmc_init();
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tegra_powergate_init();
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tegra20_hotplug_init();
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}
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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void __init tegra30_init_early(void)
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{
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tegra_cpu_reset_handler_init();
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tegra_apb_io_init();
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tegra_init_fuse();
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tegra_init_cache();
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tegra_pmc_init();
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tegra_powergate_init();
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tegra30_hotplug_init();
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}
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#endif
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void __init tegra_init_late(void)
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{
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tegra_powergate_debugfs_init();
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}
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