5c7b1aaf13
In a typical memory tiering system, there's no CPU in slow (PMEM) NUMA nodes. But if the number of the hint page faults on a PMEM node is the max for a task, The current NUMA balancing policy may try to place the task on the PMEM node instead of DRAM node. This is unreasonable, because there's no CPU in PMEM NUMA nodes. To fix this, CPU-less nodes are ignored when searching the migration target node for a task in this patch. To test the patch, we run a workload that accesses more memory in PMEM node than memory in DRAM node. Without the patch, the PMEM node will be chosen as preferred node in task_numa_placement(). While the DRAM node will be chosen instead with the patch. Signed-off-by: "Huang, Ying" <ying.huang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20220214121553.582248-2-ying.huang@intel.com |
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.. | ||
autogroup.c | ||
autogroup.h | ||
clock.c | ||
completion.c | ||
core_sched.c | ||
core.c | ||
cpuacct.c | ||
cpudeadline.c | ||
cpudeadline.h | ||
cpufreq_schedutil.c | ||
cpufreq.c | ||
cpupri.c | ||
cpupri.h | ||
cputime.c | ||
deadline.c | ||
debug.c | ||
fair.c | ||
features.h | ||
idle.c | ||
isolation.c | ||
loadavg.c | ||
Makefile | ||
membarrier.c | ||
pelt.c | ||
pelt.h | ||
psi.c | ||
rt.c | ||
sched-pelt.h | ||
sched.h | ||
smp.h | ||
stats.c | ||
stats.h | ||
stop_task.c | ||
swait.c | ||
topology.c | ||
wait_bit.c | ||
wait.c |