90039f3773
Otherwise some configurations fail.
Fixes: 0277263659 ("clk: qcom: add the driver for the MSM8996 APCS clocks")
Link: https://lore.kernel.org/r/20230223013847.1218900-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Qualcomm APCS clock controller driver
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*
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* Copyright (c) 2022, Linaro Limited
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* Author: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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*/
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#define APCS_AUX_OFFSET 0x50
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#define APCS_AUX_DIV_MASK GENMASK(17, 16)
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#define APCS_AUX_DIV_2 0x1
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static int qcom_apcs_msm8996_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device *parent = dev->parent;
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struct regmap *regmap;
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struct clk_hw *hw;
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unsigned int val;
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int ret = -ENODEV;
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regmap = dev_get_regmap(parent, NULL);
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if (!regmap) {
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dev_err(dev, "failed to get regmap: %d\n", ret);
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return ret;
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}
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regmap_read(regmap, APCS_AUX_OFFSET, &val);
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regmap_update_bits(regmap, APCS_AUX_OFFSET, APCS_AUX_DIV_MASK,
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FIELD_PREP(APCS_AUX_DIV_MASK, APCS_AUX_DIV_2));
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/*
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* This clock is used during CPU cluster setup while setting up CPU PLLs.
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* Add hardware mandated delay to make sure that the sys_apcs_aux clock
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* is stable (after setting the divider) before continuing
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* bootstrapping to keep CPUs from ending up in a weird state.
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*/
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udelay(5);
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/*
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* As this clocks is a parent of the CPU cluster clocks and is actually
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* used as a parent during CPU clocks setup, we want for it to register
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* as early as possible, without letting fw_devlink to delay probing of
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* either of the drivers.
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*
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* The sys_apcs_aux is a child (divider) of gpll0, but we register it
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* as a fixed rate clock instead to ease bootstrapping procedure. By
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* doing this we make sure that CPU cluster clocks are able to be setup
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* early during the boot process (as it is recommended by Qualcomm).
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*/
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hw = devm_clk_hw_register_fixed_rate(dev, "sys_apcs_aux", NULL, 0, 300000000);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
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}
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static struct platform_driver qcom_apcs_msm8996_clk_driver = {
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.probe = qcom_apcs_msm8996_clk_probe,
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.driver = {
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.name = "qcom-apcs-msm8996-clk",
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},
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};
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/* Register early enough to fix the clock to be used for other cores */
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static int __init qcom_apcs_msm8996_clk_init(void)
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{
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return platform_driver_register(&qcom_apcs_msm8996_clk_driver);
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}
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postcore_initcall(qcom_apcs_msm8996_clk_init);
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static void __exit qcom_apcs_msm8996_clk_exit(void)
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{
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platform_driver_unregister(&qcom_apcs_msm8996_clk_driver);
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}
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module_exit(qcom_apcs_msm8996_clk_exit);
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MODULE_AUTHOR("Dmitry Baryshkov <dmitry.baryshkov@linaro.org>");
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Qualcomm MSM8996 APCS clock driver");
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