93f21d925f
Configure the disable wait value on the CX GDSC to ensure we don't get
any undefined behavior. This was omitted when first adding the driver.
Fixes: 8397e24278 ("clk: qcom: Add GPU clock controller driver for SM6375")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230329140135.2178957-1-konrad.dybcio@linaro.org
459 lines
11 KiB
C
459 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,sm6375-gpucc.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "clk-regmap-phy-mux.h"
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#include "gdsc.h"
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#include "reset.h"
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enum {
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DT_BI_TCXO,
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DT_GCC_GPU_GPLL0_CLK_SRC,
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DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
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DT_GCC_GPU_SNOC_DVM_GFX_CLK,
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};
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enum {
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P_BI_TCXO,
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P_GCC_GPU_GPLL0_CLK_SRC,
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P_GCC_GPU_GPLL0_DIV_CLK_SRC,
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P_GPU_CC_PLL0_OUT_EVEN,
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P_GPU_CC_PLL0_OUT_MAIN,
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P_GPU_CC_PLL0_OUT_ODD,
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P_GPU_CC_PLL1_OUT_EVEN,
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P_GPU_CC_PLL1_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_ODD,
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};
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static struct pll_vco lucid_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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/* 532MHz Configuration */
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static const struct alpha_pll_config gpucc_pll0_config = {
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.l = 0x1b,
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.alpha = 0xb555,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002261,
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.config_ctl_hi1_val = 0x329a299c,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x00000000,
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};
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static struct clk_alpha_pll gpucc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_vco,
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.num_vco = ARRAY_SIZE(lucid_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.index = P_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_ops,
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},
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},
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};
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/* 514MHz Configuration */
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static const struct alpha_pll_config gpucc_pll1_config = {
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.l = 0x1a,
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.alpha = 0xc555,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002261,
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.config_ctl_hi1_val = 0x329a299c,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x00000000,
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};
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static struct clk_alpha_pll gpucc_pll1 = {
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.offset = 0x100,
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.vco_table = lucid_vco,
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.num_vco = ARRAY_SIZE(lucid_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_pll1",
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.parent_data = &(const struct clk_parent_data){
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.index = P_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_ops,
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},
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},
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};
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static const struct parent_map gpucc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
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{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
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};
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static const struct clk_parent_data gpucc_parent_data_0[] = {
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{ .index = P_BI_TCXO },
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{ .hw = &gpucc_pll0.clkr.hw },
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{ .hw = &gpucc_pll1.clkr.hw },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
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};
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static const struct parent_map gpucc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_EVEN, 1 },
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{ P_GPU_CC_PLL0_OUT_ODD, 2 },
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{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
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{ P_GPU_CC_PLL1_OUT_ODD, 4 },
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{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
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};
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static const struct clk_parent_data gpucc_parent_data_1[] = {
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{ .index = P_BI_TCXO },
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{ .hw = &gpucc_pll0.clkr.hw },
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{ .hw = &gpucc_pll0.clkr.hw },
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{ .hw = &gpucc_pll1.clkr.hw },
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{ .hw = &gpucc_pll1.clkr.hw },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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};
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static const struct freq_tbl ftbl_gpucc_gmu_clk_src[] = {
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F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpucc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpucc_parent_map_0,
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.freq_tbl = ftbl_gpucc_gmu_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpucc_gmu_clk_src",
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.parent_data = gpucc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpucc_parent_data_0),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_gpucc_gx_gfx3d_clk_src[] = {
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F(266000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(390000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(490000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(770000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(840000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(900000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpucc_gx_gfx3d_clk_src = {
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.cmd_rcgr = 0x101c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpucc_parent_map_1,
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.freq_tbl = ftbl_gpucc_gx_gfx3d_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpucc_gx_gfx3d_clk_src",
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.parent_data = gpucc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpucc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch gpucc_ahb_clk = {
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.halt_reg = 0x1078,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1078,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_cx_gfx3d_clk = {
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.halt_reg = 0x10a4,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x10a4,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_cx_gfx3d_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpucc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_cx_gfx3d_slv_clk = {
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.halt_reg = 0x10a8,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x10a8,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_cx_gfx3d_slv_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpucc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_cx_gmu_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_cx_gmu_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpucc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_cx_snoc_dvm_clk = {
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.halt_reg = 0x108c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x108c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_cx_snoc_dvm_clk",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_GCC_GPU_SNOC_DVM_GFX_CLK,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_cxo_aon_clk = {
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.halt_reg = 0x1004,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_cxo_aon_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_cxo_clk = {
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.halt_reg = 0x109c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x109c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_cxo_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_gx_cxo_clk = {
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.halt_reg = 0x1060,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1060,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_gx_cxo_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_gx_gfx3d_clk = {
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.halt_reg = 0x1054,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1054,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_gx_gfx3d_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpucc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_gx_gmu_clk = {
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.halt_reg = 0x1064,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1064,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_gx_gmu_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpucc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_sleep_clk = {
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.halt_reg = 0x1090,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x1090,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_sleep_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc gpu_cx_gdsc = {
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.gdscr = 0x106c,
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.gds_hw_ctrl = 0x1540,
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.clk_dis_wait_val = 8,
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.pd = {
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.name = "gpu_cx_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = VOTABLE,
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};
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static struct gdsc gpu_gx_gdsc = {
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.gdscr = 0x100c,
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.clamp_io_ctrl = 0x1508,
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.resets = (unsigned int []){ GPU_GX_BCR, GPU_ACD_BCR, GPU_GX_ACD_MISC_BCR },
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.reset_count = 3,
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.pd = {
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.name = "gpu_gx_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = CLAMP_IO | SW_RESET | AON_RESET,
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};
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static struct clk_regmap *gpucc_sm6375_clocks[] = {
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[GPU_CC_AHB_CLK] = &gpucc_ahb_clk.clkr,
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[GPU_CC_CX_GFX3D_CLK] = &gpucc_cx_gfx3d_clk.clkr,
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[GPU_CC_CX_GFX3D_SLV_CLK] = &gpucc_cx_gfx3d_slv_clk.clkr,
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[GPU_CC_CX_GMU_CLK] = &gpucc_cx_gmu_clk.clkr,
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[GPU_CC_CX_SNOC_DVM_CLK] = &gpucc_cx_snoc_dvm_clk.clkr,
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[GPU_CC_CXO_AON_CLK] = &gpucc_cxo_aon_clk.clkr,
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[GPU_CC_CXO_CLK] = &gpucc_cxo_clk.clkr,
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[GPU_CC_GMU_CLK_SRC] = &gpucc_gmu_clk_src.clkr,
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[GPU_CC_GX_CXO_CLK] = &gpucc_gx_cxo_clk.clkr,
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[GPU_CC_GX_GFX3D_CLK] = &gpucc_gx_gfx3d_clk.clkr,
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[GPU_CC_GX_GFX3D_CLK_SRC] = &gpucc_gx_gfx3d_clk_src.clkr,
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[GPU_CC_GX_GMU_CLK] = &gpucc_gx_gmu_clk.clkr,
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[GPU_CC_PLL0] = &gpucc_pll0.clkr,
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[GPU_CC_PLL1] = &gpucc_pll1.clkr,
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[GPU_CC_SLEEP_CLK] = &gpucc_sleep_clk.clkr,
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};
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static const struct qcom_reset_map gpucc_sm6375_resets[] = {
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[GPU_GX_BCR] = { 0x1008 },
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[GPU_ACD_BCR] = { 0x1160 },
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[GPU_GX_ACD_MISC_BCR] = { 0x8004 },
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};
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static struct gdsc *gpucc_sm6375_gdscs[] = {
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[GPU_CX_GDSC] = &gpu_cx_gdsc,
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[GPU_GX_GDSC] = &gpu_gx_gdsc,
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};
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static const struct regmap_config gpucc_sm6375_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x9000,
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.fast_io = true,
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};
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static const struct qcom_cc_desc gpucc_sm6375_desc = {
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.config = &gpucc_sm6375_regmap_config,
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.clks = gpucc_sm6375_clocks,
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.num_clks = ARRAY_SIZE(gpucc_sm6375_clocks),
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.resets = gpucc_sm6375_resets,
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.num_resets = ARRAY_SIZE(gpucc_sm6375_resets),
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.gdscs = gpucc_sm6375_gdscs,
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.num_gdscs = ARRAY_SIZE(gpucc_sm6375_gdscs),
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};
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static const struct of_device_id gpucc_sm6375_match_table[] = {
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{ .compatible = "qcom,sm6375-gpucc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, gpucc_sm6375_match_table);
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static int gpucc_sm6375_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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regmap = qcom_cc_map(pdev, &gpucc_sm6375_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config);
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clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config);
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return qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap);
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}
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static struct platform_driver gpucc_sm6375_driver = {
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.probe = gpucc_sm6375_probe,
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.driver = {
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.name = "gpucc-sm6375",
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.of_match_table = gpucc_sm6375_match_table,
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},
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|
};
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module_platform_driver(gpucc_sm6375_driver);
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|
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MODULE_DESCRIPTION("QTI GPUCC SM6375 Driver");
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MODULE_LICENSE("GPL");
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