UAPI Changes: - Weak parallel submission support for execlists Minimal implementation of the parallel submission support for execlists backend that was previously only implemented for GuC. Support one sibling non-virtual engine. Core Changes: - Two backmerges of drm/drm-next for header file renames/changes and i915_regs reorganization Driver Changes: - Add new DG2 subplatform: DG2-G12 (Matt R) - Add new DG2 workarounds (Matt R, Ram, Bruce) - Handle pre-programmed WOPCM registers for DG2+ (Daniele) - Update guc shim control programming on XeHP SDV+ (Daniele) - Add RPL-S C0/D0 stepping information (Anusha) - Improve GuC ADS initialization to work on ARM64 on dGFX (Lucas) - Fix KMD and GuC race on accessing PMU busyness (Umesh) - Use PM timestamp instead of RING TIMESTAMP for reference in PMU with GuC (Umesh) - Report error on invalid reset notification from GuC (John) - Avoid WARN splat by holding RPM wakelock during PXP unbind (Juston) - Fixes to parallel submission implementation (Matt B.) - Improve GuC loading status check/error reports (John) - Tweak TTM LRU priority hint selection (Matt A.) - Align the plane_vma to min_page_size of stolen mem (Ram) - Introduce vma resources and implement async unbinding (Thomas) - Use struct vma_resource instead of struct vma_snapshot (Thomas) - Return some TTM accel move errors instead of trying memcpy move (Thomas) - Fix a race between vma / object destruction and unbinding (Thomas) - Remove short-term pins from execbuf (Maarten) - Update to GuC version 69.0.3 (John, Michal Wa.) - Improvements to GT reset paths in GuC backend (Matt B.) - Use shrinker_release_pages instead of writeback in shmem object hooks (Matt A., Tvrtko) - Use trylock instead of blocking lock when freeing GEM objects (Maarten) - Allocate intel_engine_coredump_alloc with ALLOW_FAIL (Matt B.) - Fixes to object unmapping and purging (Matt A) - Check for wedged device in GuC backend (John) - Avoid lockdep splat by locking dpt_obj around set_cache_level (Maarten) - Allow dead vm to unbind vma's without lock (Maarten) - s/engine->i915/i915/ for DG2 engine workarounds (Matt R) - Use to_gt() helper for GGTT accesses (Michal Wi.) - Selftest improvements (Matt B., Thomas, Ram) - Coding style and compiler warning fixes (Matt B., Jasmine, Andi, Colin, Gustavo, Dan) From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/Yg4i2aCZvvee5Eai@jlahtine-mobl.ger.corp.intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [Fixed conflicts while applying, using the fixups/drm-intel-gt-next.patch from drm-rerere's 1f2b1742abdd ("2022y-02m-23d-16h-07m-57s UTC: drm-tip rerere cache update")]
43 lines
1.4 KiB
C
43 lines
1.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DP_LINK_TRAINING_H__
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#define __INTEL_DP_LINK_TRAINING_H__
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#include <drm/dp/drm_dp_helper.h>
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struct intel_crtc_state;
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struct intel_dp;
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int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
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void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy,
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const u8 link_status[DP_LINK_STATUS_SIZE]);
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void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy,
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u8 dp_train_pat);
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void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy);
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void intel_dp_start_link_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void intel_dp_stop_link_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void
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intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
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const u8 link_status[DP_LINK_STATUS_SIZE]);
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/* Get the TPSx symbol type of the value programmed to DP_TRAINING_PATTERN_SET */
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static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
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{
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return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
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}
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#endif /* __INTEL_DP_LINK_TRAINING_H__ */
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