f8fd5c2483
changes to the clk framework this time around. That's probably because everyone was on vacation (yours truly included). We did lose a couple clk drivers this time around because nobody was using those devices. That skews the diffstat a bit, but either way, nothing looks out of the ordinary here. The usual suspects are chugging along adding support for more SoCs and fixing bugs. If I had to choose, I'd say the theme for the past few months has been "polish". There's quite a few patches that migrate to devm_platform_ioremap_resource() in here. And there's more than a handful of patches that move the NR_CLKS define from the DT binding header to the driver. There's even patches that migrate drivers to use clk_parent_data and clk_hw to describe clk tree topology. It seems that the spring (summer?) cleaning bug got some folks, or the semiconductor shortage finally hit the software side. New Drivers: - StarFive JH7110 SoC clock drivers - Qualcomm IPQ5018 Global Clock Controller driver - Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK Removed Drivers: - Remove non-OF mmp clk drivers - Remove OXNAS clk driver Updates: - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Move defines for numbers of clks (NR_CLKS) from DT headers to drivers - Introduce kstrdup_and_replace() and use it - Add PLL rates for Rockchip rk3568 - Add the display clock tree for Rockchip rv1126 - Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and RZ/G2 SoCs - Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource() - Fix function name in a comment in ccu_mmc_timing.c - Parameter name correction for ccu_nkm_round_rate() - Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e. consider alternative parent rates when determining clock rates - Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi - Support finding closest (as opposed to closest but not higher) clock rate for NM, NKM, mux and div type clocks, as use it for Allwinner A64 pll-video0 - Prefer current parent rate if able to generate ideal clock rate for Allwinner NKM clocks - Clean up Qualcomm SMD RPM driver, with interconnect bus clocks moved out to the interconnect drivers - Fix various PM runtime bugs across many Qualcomm clk drivers - Migrate Qualcomm MDM9615 is to parent_hw and parent_data - Add network related resets on Qualcomm IPQ4019 - Add a couple missing USB related clocks to Qualcomm IPQ9574 - Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock controller - In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs, and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are corrected - Add missing GDSCs to and correct GDSCs for the SC8280XP global clock controller driver - Support retention for the Qualcomm SC8280XP display clock controller GDSCs. - Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE to fix issues with missing parent clocks across sc7180, sm7150, sm6350 and sm8250, while sm8450 is corrected to use floor ops - Correct Qualcomm SM6350 GPU clock controller's clock supplies - Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver - Add missing OXILICX GDSC to Qualcomm MSM8226 GCC - Change the delay in the Qualcomm reset controller to fsleep() for correctness - Extend the Qualcomm SM83550 Video clock controller to support SC8280XP - Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3, M3-W, and M3-N SoCs - Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M - Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five - Add the PDM IPC clock for i.MX93 - Add 519.75MHz frequency support for i.MX9 PLL - Simplify the .determine_rate() implementation for i.MX GPR mux - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource() - Add the audio mux clock to i.MX8 - Fix the SPLL2 MULT range for PLLv4 - Update the SPLL2 type in i.MX8ULP - Fix the SAI4 clock on i.MX8MP - Add silicon revision print for i.MX25 on clocks init - Drop the return value from __mx25_clocks_init() - Fix the clock pauses on no-op set_rate for i.MX8M composite clock - Drop restrictions for i.MX PLL14xx and fix its max prediv value - Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to allow glitch free switching -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmTv2wkRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSW1LRAAuHR2HoyB4bRHmCa1bfOfYYDfSWsBWEav tWIfBl86Nl/Je50Gk2NJ9vqU5OPqRZ57TIniijHHoX5n7/kYcr8KVmlomY07hUeg CzWyothkxg4k7+rQwVAWvmlR2YAVwzHDKcwq7gkMZOnW/y26LXip99cjopu2CJLx zVwTgvWollmd4KVlicnAlx4zUjgNkWR24iA4Lcf5ir+Dr6FYNjxLI+akBA8EPxxi wLixZbScgBSgpGn6KVgoFhclCToPS0gt5m6HfQxJ/svOCU54l+jRKpzkNZGWvyu4 A8t3CRrwL2iS/mfCGk2yRlaKySoLLpjlpW1AI7fHTWbG2P6p8ZphtN7jOeeAEsbq TNpzWEjtY6B/lfRzxxINXkrtLaqmlnFY/P5np5fDrf/61gRFxLFQemyRdY/xCSJf Kwq8ja1mrSGWoDGG9XhDqTf9Yek9LRObNzlDrEmn/i/qLTcxhOIz58pzHg4iAlx5 9HDtnJ8hKg4uE1TtT12Bmasb1+WzG7GYYESNfKWZhCvbRqEUzcDOHk7xpwYa1ffx yZIgMs7Sb/exNW8LMPYmgnyj/f9eo5IdjiQvune+Zy5NrdzfyN6Sf/LSibrqCF2z X5aFHqQrR8+PifD+se+g5HPa0ezSmBIhXzYUTOC6f+nywlrJjhwDXPDYI6Lcd//p r4mpOmJS+G4= =h2Jz -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk subsystem updates from Stephen Boyd: "This pull request is full of clk driver changes. In fact, there aren't any changes to the clk framework this time around. That's probably because everyone was on vacation (yours truly included). We did lose a couple clk drivers this time around because nobody was using those devices. That skews the diffstat a bit, but either way, nothing looks out of the ordinary here. The usual suspects are chugging along adding support for more SoCs and fixing bugs. If I had to choose, I'd say the theme for the past few months has been "polish". There's quite a few patches that migrate to devm_platform_ioremap_resource() in here. And there's more than a handful of patches that move the NR_CLKS define from the DT binding header to the driver. There's even patches that migrate drivers to use clk_parent_data and clk_hw to describe clk tree topology. It seems that the spring (summer?) cleaning bug got some folks, or the semiconductor shortage finally hit the software side. New Drivers: - StarFive JH7110 SoC clock drivers - Qualcomm IPQ5018 Global Clock Controller driver - Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK Removed Drivers: - Remove non-OF mmp clk drivers - Remove OXNAS clk driver Updates: - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Move defines for numbers of clks (NR_CLKS) from DT headers to drivers - Introduce kstrdup_and_replace() and use it - Add PLL rates for Rockchip rk3568 - Add the display clock tree for Rockchip rv1126 - Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and RZ/G2 SoCs - Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource() - Fix function name in a comment in ccu_mmc_timing.c - Parameter name correction for ccu_nkm_round_rate() - Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e. consider alternative parent rates when determining clock rates - Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi - Support finding closest (as opposed to closest but not higher) clock rate for NM, NKM, mux and div type clocks, as use it for Allwinner A64 pll-video0 - Prefer current parent rate if able to generate ideal clock rate for Allwinner NKM clocks - Clean up Qualcomm SMD RPM driver, with interconnect bus clocks moved out to the interconnect drivers - Fix various PM runtime bugs across many Qualcomm clk drivers - Migrate Qualcomm MDM9615 is to parent_hw and parent_data - Add network related resets on Qualcomm IPQ4019 - Add a couple missing USB related clocks to Qualcomm IPQ9574 - Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock controller - In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs, and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are corrected - Add missing GDSCs to and correct GDSCs for the SC8280XP global clock controller driver - Support retention for the Qualcomm SC8280XP display clock controller GDSCs. - Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE to fix issues with missing parent clocks across sc7180, sm7150, sm6350 and sm8250, while sm8450 is corrected to use floor ops - Correct Qualcomm SM6350 GPU clock controller's clock supplies - Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver - Add missing OXILICX GDSC to Qualcomm MSM8226 GCC - Change the delay in the Qualcomm reset controller to fsleep() for correctness - Extend the Qualcomm SM83550 Video clock controller to support SC8280XP - Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3, M3-W, and M3-N SoCs - Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M - Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five - Add the PDM IPC clock for i.MX93 - Add 519.75MHz frequency support for i.MX9 PLL - Simplify the .determine_rate() implementation for i.MX GPR mux - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource() - Add the audio mux clock to i.MX8 - Fix the SPLL2 MULT range for PLLv4 - Update the SPLL2 type in i.MX8ULP - Fix the SAI4 clock on i.MX8MP - Add silicon revision print for i.MX25 on clocks init - Drop the return value from __mx25_clocks_init() - Fix the clock pauses on no-op set_rate for i.MX8M composite clock - Drop restrictions for i.MX PLL14xx and fix its max prediv value - Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to allow glitch free switching" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (207 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source ...
250 lines
5.9 KiB
C
250 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015, Sony Mobile Communications AB.
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* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/rpmsg.h>
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#include <linux/soc/qcom/smd-rpm.h>
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#define RPM_REQUEST_TIMEOUT (5 * HZ)
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/**
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* struct qcom_smd_rpm - state of the rpm device driver
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* @rpm_channel: reference to the smd channel
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* @dev: rpm device
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* @ack: completion for acks
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* @lock: mutual exclusion around the send/complete pair
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* @ack_status: result of the rpm request
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*/
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struct qcom_smd_rpm {
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struct rpmsg_endpoint *rpm_channel;
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struct device *dev;
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struct completion ack;
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struct mutex lock;
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int ack_status;
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};
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/**
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* struct qcom_rpm_header - header for all rpm requests and responses
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* @service_type: identifier of the service
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* @length: length of the payload
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*/
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struct qcom_rpm_header {
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__le32 service_type;
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__le32 length;
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};
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/**
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* struct qcom_rpm_request - request message to the rpm
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* @msg_id: identifier of the outgoing message
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* @flags: active/sleep state flags
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* @type: resource type
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* @id: resource id
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* @data_len: length of the payload following this header
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*/
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struct qcom_rpm_request {
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__le32 msg_id;
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__le32 flags;
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__le32 type;
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__le32 id;
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__le32 data_len;
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};
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/**
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* struct qcom_rpm_message - response message from the rpm
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* @msg_type: indicator of the type of message
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* @length: the size of this message, including the message header
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* @msg_id: message id
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* @message: textual message from the rpm
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*
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* Multiple of these messages can be stacked in an rpm message.
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*/
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struct qcom_rpm_message {
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__le32 msg_type;
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__le32 length;
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union {
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__le32 msg_id;
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DECLARE_FLEX_ARRAY(u8, message);
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};
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};
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#define RPM_SERVICE_TYPE_REQUEST 0x00716572 /* "req\0" */
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#define RPM_MSG_TYPE_ERR 0x00727265 /* "err\0" */
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#define RPM_MSG_TYPE_MSG_ID 0x2367736d /* "msg#" */
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/**
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* qcom_rpm_smd_write - write @buf to @type:@id
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* @rpm: rpm handle
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* @state: active/sleep state flags
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* @type: resource type
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* @id: resource identifier
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* @buf: the data to be written
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* @count: number of bytes in @buf
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*/
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int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
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int state,
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u32 type, u32 id,
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void *buf,
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size_t count)
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{
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static unsigned msg_id = 1;
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int left;
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int ret;
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struct {
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struct qcom_rpm_header hdr;
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struct qcom_rpm_request req;
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u8 payload[];
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} *pkt;
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size_t size = sizeof(*pkt) + count;
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/* SMD packets to the RPM may not exceed 256 bytes */
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if (WARN_ON(size >= 256))
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return -EINVAL;
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pkt = kmalloc(size, GFP_ATOMIC);
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if (!pkt)
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return -ENOMEM;
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mutex_lock(&rpm->lock);
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pkt->hdr.service_type = cpu_to_le32(RPM_SERVICE_TYPE_REQUEST);
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pkt->hdr.length = cpu_to_le32(sizeof(struct qcom_rpm_request) + count);
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pkt->req.msg_id = cpu_to_le32(msg_id++);
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pkt->req.flags = cpu_to_le32(state);
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pkt->req.type = cpu_to_le32(type);
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pkt->req.id = cpu_to_le32(id);
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pkt->req.data_len = cpu_to_le32(count);
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memcpy(pkt->payload, buf, count);
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ret = rpmsg_send(rpm->rpm_channel, pkt, size);
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if (ret)
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goto out;
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left = wait_for_completion_timeout(&rpm->ack, RPM_REQUEST_TIMEOUT);
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if (!left)
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ret = -ETIMEDOUT;
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else
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ret = rpm->ack_status;
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out:
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kfree(pkt);
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mutex_unlock(&rpm->lock);
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return ret;
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}
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EXPORT_SYMBOL(qcom_rpm_smd_write);
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static int qcom_smd_rpm_callback(struct rpmsg_device *rpdev,
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void *data,
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int count,
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void *priv,
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u32 addr)
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{
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const struct qcom_rpm_header *hdr = data;
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size_t hdr_length = le32_to_cpu(hdr->length);
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const struct qcom_rpm_message *msg;
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struct qcom_smd_rpm *rpm = dev_get_drvdata(&rpdev->dev);
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const u8 *buf = data + sizeof(struct qcom_rpm_header);
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const u8 *end = buf + hdr_length;
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char msgbuf[32];
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int status = 0;
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u32 len, msg_length;
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if (le32_to_cpu(hdr->service_type) != RPM_SERVICE_TYPE_REQUEST ||
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hdr_length < sizeof(struct qcom_rpm_message)) {
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dev_err(rpm->dev, "invalid request\n");
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return 0;
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}
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while (buf < end) {
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msg = (struct qcom_rpm_message *)buf;
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msg_length = le32_to_cpu(msg->length);
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switch (le32_to_cpu(msg->msg_type)) {
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case RPM_MSG_TYPE_MSG_ID:
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break;
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case RPM_MSG_TYPE_ERR:
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len = min_t(u32, ALIGN(msg_length, 4), sizeof(msgbuf));
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memcpy_fromio(msgbuf, msg->message, len);
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msgbuf[len - 1] = 0;
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if (!strcmp(msgbuf, "resource does not exist"))
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status = -ENXIO;
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else
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status = -EINVAL;
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break;
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}
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buf = PTR_ALIGN(buf + 2 * sizeof(u32) + msg_length, 4);
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}
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rpm->ack_status = status;
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complete(&rpm->ack);
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return 0;
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}
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static int qcom_smd_rpm_probe(struct rpmsg_device *rpdev)
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{
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struct qcom_smd_rpm *rpm;
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if (!rpdev->dev.of_node)
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return -EINVAL;
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rpm = devm_kzalloc(&rpdev->dev, sizeof(*rpm), GFP_KERNEL);
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if (!rpm)
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return -ENOMEM;
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mutex_init(&rpm->lock);
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init_completion(&rpm->ack);
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rpm->dev = &rpdev->dev;
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rpm->rpm_channel = rpdev->ept;
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dev_set_drvdata(&rpdev->dev, rpm);
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return of_platform_populate(rpdev->dev.of_node, NULL, NULL, &rpdev->dev);
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}
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static void qcom_smd_rpm_remove(struct rpmsg_device *rpdev)
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{
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of_platform_depopulate(&rpdev->dev);
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}
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static const struct rpmsg_device_id qcom_smd_rpm_id_table[] = {
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{ .name = "rpm_requests", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(rpmsg, qcom_smd_rpm_id_table);
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static struct rpmsg_driver qcom_smd_rpm_driver = {
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.probe = qcom_smd_rpm_probe,
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.remove = qcom_smd_rpm_remove,
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.callback = qcom_smd_rpm_callback,
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.id_table = qcom_smd_rpm_id_table,
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.drv.name = "qcom_smd_rpm",
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};
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static int __init qcom_smd_rpm_init(void)
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{
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return register_rpmsg_driver(&qcom_smd_rpm_driver);
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}
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arch_initcall(qcom_smd_rpm_init);
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static void __exit qcom_smd_rpm_exit(void)
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{
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unregister_rpmsg_driver(&qcom_smd_rpm_driver);
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}
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module_exit(qcom_smd_rpm_exit);
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MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
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MODULE_DESCRIPTION("Qualcomm SMD backed RPM driver");
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MODULE_LICENSE("GPL v2");
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