Martin Blumenstingl 5dbe7890e6 clk: gxbb: expose USB clocks ...

USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related
dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs.
Expose these clocks to DT and comment out in clk driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

2016-09-14 11:23:55 -07:00

..

clk-cpu.c

clk: meson8b: clean up cpu clocks

2016-06-22 18:02:35 -07:00

clk-mpll.c

clk: meson: add mpll support

2016-06-22 18:02:59 -07:00

clk-pll.c

clk: meson: fractional pll support

2016-06-22 18:05:47 -07:00

clkc.h

gxbb: clk: Adjust MESON_GATE macro to be shared with meson8b

2016-09-01 17:42:41 -07:00

gxbb-aoclk.c

clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe()

2016-08-24 00:55:13 -07:00

gxbb.c

gxbb: clk: Adjust MESON_GATE macro to be shared with meson8b

2016-09-01 17:42:41 -07:00

gxbb.h

clk: gxbb: expose USB clocks

2016-09-14 11:23:55 -07:00

Kconfig

clk: gxbb: add AmLogic GXBB clk controller driver

2016-06-22 18:07:31 -07:00

Makefile

clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention

2016-09-01 17:31:44 -07:00

meson8b.c

meson: clk: Add support for clock gates

2016-09-01 17:43:12 -07:00

meson8b.h

meson: clk: Add support for clock gates

2016-09-01 17:43:12 -07:00