Vladimir Zapolskiy e4e6448638 cpufreq: qcom-cpufreq-hw: Clear dcvs interrupts
It's noted that dcvs interrupts are not self-clearing, thus an interrupt
handler runs constantly, which leads to a severe regression in runtime.
To fix the problem an explicit write to clear interrupt register is
required, note that on OSM platforms the register may not be present.

Fixes: 275157b367f4 ("cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-04-26 12:08:31 +05:30
..
2019-07-18 09:49:30 +02:00
2019-07-18 09:49:30 +02:00