fc63a6e08a
We'd like all architectures to convert to ARCH_ATOMIC, as once all
architectures are converted it will be possible to make significant
cleanups to the atomics headers, and this will make it much easier to
generically enable atomic functionality (e.g. debug logic in the
instrumented wrappers).
As a step towards that, this patch migrates alpha to ARCH_ATOMIC. The
arch code provides arch_{atomic,atomic64,xchg,cmpxchg}*(), and common
code wraps these with optional instrumentation to provide the regular
functions.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20210525140232.53872-16-mark.rutland@arm.com
28 lines
1.0 KiB
C
28 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_SYNC_BITOPS_H__
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#define __ASM_SYNC_BITOPS_H__
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#include <asm/bitops.h>
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/* sync_bitops functions are equivalent to the SMP implementation of the
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* original functions, independently from CONFIG_SMP being defined.
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*
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* We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
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* under Xen you might be communicating with a completely external entity
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* who might be on another CPU (e.g. two uniprocessor guests communicating
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* via event channels and grant tables). So we need a variant of the bit
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* ops which are SMP safe even on a UP kernel.
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*/
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#define sync_set_bit(nr, p) _set_bit(nr, p)
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#define sync_clear_bit(nr, p) _clear_bit(nr, p)
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#define sync_change_bit(nr, p) _change_bit(nr, p)
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#define sync_test_and_set_bit(nr, p) _test_and_set_bit(nr, p)
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#define sync_test_and_clear_bit(nr, p) _test_and_clear_bit(nr, p)
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#define sync_test_and_change_bit(nr, p) _test_and_change_bit(nr, p)
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#define sync_test_bit(nr, addr) test_bit(nr, addr)
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#define arch_sync_cmpxchg arch_cmpxchg
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#endif
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