Mylène Josserand 603a0c8af9 clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig
The audio DAI needs to set the clock rates of the ac-dig clock.
To make it possible, the parent PLL audio clock rates should
also be changed. This is possible via "CLK_SET_RATE_PARENT" flag.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-17 17:42:46 +01:00
..
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2016-07-08 18:05:12 -07:00
2016-11-03 09:06:18 +01:00
2016-11-03 09:06:18 +01:00
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