1c4d9d5bbb
Enable the detection of hangs by setting watchdog timers (WDTs) on generations that supports that feature. The default timeout value comes from HW specs. WTDs are reset each time an accelerator wins arbitration and is able to send/read a command to/from an accelerator. The value has added significant margin to make sure there are no spurious timeouts. The scope of watchdog is per QAT device. If a timeout is detected, the firmware resets the accelerator and returns a response descriptor with an appropriate error code. Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
236 lines
6.7 KiB
C
236 lines
6.7 KiB
C
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
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/* Copyright(c) 2020 Intel Corporation */
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#include <adf_accel_devices.h>
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#include <adf_common_drv.h>
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#include <adf_pf2vf_msg.h>
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#include <adf_gen4_hw_data.h>
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#include "adf_4xxx_hw_data.h"
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#include "icp_qat_hw.h"
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struct adf_fw_config {
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u32 ae_mask;
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char *obj_name;
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};
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static struct adf_fw_config adf_4xxx_fw_config[] = {
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{0xF0, ADF_4XXX_SYM_OBJ},
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{0xF, ADF_4XXX_ASYM_OBJ},
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{0x100, ADF_4XXX_ADMIN_OBJ},
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};
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/* Worker thread to service arbiter mappings */
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static const u32 thrd_to_arb_map[ADF_4XXX_MAX_ACCELENGINES] = {
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0x5555555, 0x5555555, 0x5555555, 0x5555555,
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0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA,
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0x0
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};
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static struct adf_hw_device_class adf_4xxx_class = {
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.name = ADF_4XXX_DEVICE_NAME,
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.type = DEV_4XXX,
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.instances = 0,
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};
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static u32 get_accel_mask(struct adf_hw_device_data *self)
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{
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return ADF_4XXX_ACCELERATORS_MASK;
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}
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static u32 get_ae_mask(struct adf_hw_device_data *self)
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{
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u32 me_disable = self->fuses;
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return ~me_disable & ADF_4XXX_ACCELENGINES_MASK;
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}
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static u32 get_num_accels(struct adf_hw_device_data *self)
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{
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return ADF_4XXX_MAX_ACCELERATORS;
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}
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static u32 get_num_aes(struct adf_hw_device_data *self)
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{
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if (!self || !self->ae_mask)
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return 0;
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return hweight32(self->ae_mask);
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}
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static u32 get_misc_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_4XXX_PMISC_BAR;
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}
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static u32 get_etr_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_4XXX_ETR_BAR;
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}
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static u32 get_sram_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_4XXX_SRAM_BAR;
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}
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/*
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* The vector routing table is used to select the MSI-X entry to use for each
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* interrupt source.
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* The first ADF_4XXX_ETR_MAX_BANKS entries correspond to ring interrupts.
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* The final entry corresponds to VF2PF or error interrupts.
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* This vector table could be used to configure one MSI-X entry to be shared
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* between multiple interrupt sources.
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*
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* The default routing is set to have a one to one correspondence between the
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* interrupt source and the MSI-X entry used.
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*/
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static void set_msix_default_rttable(struct adf_accel_dev *accel_dev)
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{
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void __iomem *csr;
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int i;
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csr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr;
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for (i = 0; i <= ADF_4XXX_ETR_MAX_BANKS; i++)
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ADF_CSR_WR(csr, ADF_4XXX_MSIX_RTTABLE_OFFSET(i), i);
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}
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static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
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{
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struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
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u32 fusectl1;
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u32 capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
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ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
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ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
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ICP_ACCEL_CAPABILITIES_AES_V2;
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/* Read accelerator capabilities mask */
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pci_read_config_dword(pdev, ADF_4XXX_FUSECTL1_OFFSET, &fusectl1);
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if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE)
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
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if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE)
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capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
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if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE)
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
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return capabilities;
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}
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static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
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{
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return DEV_SKU_1;
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}
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static const u32 *adf_get_arbiter_mapping(void)
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{
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return thrd_to_arb_map;
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}
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static void get_arb_info(struct arb_info *arb_info)
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{
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arb_info->arb_cfg = ADF_4XXX_ARB_CONFIG;
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arb_info->arb_offset = ADF_4XXX_ARB_OFFSET;
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arb_info->wt2sam_offset = ADF_4XXX_ARB_WRK_2_SER_MAP_OFFSET;
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}
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static void get_admin_info(struct admin_info *admin_csrs_info)
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{
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admin_csrs_info->mailbox_offset = ADF_4XXX_MAILBOX_BASE_OFFSET;
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admin_csrs_info->admin_msg_ur = ADF_4XXX_ADMINMSGUR_OFFSET;
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admin_csrs_info->admin_msg_lr = ADF_4XXX_ADMINMSGLR_OFFSET;
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}
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static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
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{
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struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR];
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void __iomem *csr = misc_bar->virt_addr;
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/* Enable all in errsou3 except VFLR notification on host */
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ADF_CSR_WR(csr, ADF_4XXX_ERRMSK3, ADF_4XXX_VFLNOTIFY);
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}
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static void adf_enable_ints(struct adf_accel_dev *accel_dev)
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{
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void __iomem *addr;
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addr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr;
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/* Enable bundle interrupts */
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ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X0_MASK_OFFSET, 0);
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ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X1_MASK_OFFSET, 0);
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/* Enable misc interrupts */
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ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_MASK_OFFSET, 0);
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}
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static int adf_pf_enable_vf2pf_comms(struct adf_accel_dev *accel_dev)
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{
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return 0;
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}
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static u32 uof_get_num_objs(void)
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{
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return ARRAY_SIZE(adf_4xxx_fw_config);
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}
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static char *uof_get_name(u32 obj_num)
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{
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return adf_4xxx_fw_config[obj_num].obj_name;
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}
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static u32 uof_get_ae_mask(u32 obj_num)
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{
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return adf_4xxx_fw_config[obj_num].ae_mask;
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}
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void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class = &adf_4xxx_class;
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hw_data->instance_id = adf_4xxx_class.instances++;
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hw_data->num_banks = ADF_4XXX_ETR_MAX_BANKS;
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hw_data->num_rings_per_bank = ADF_4XXX_NUM_RINGS_PER_BANK;
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hw_data->num_accel = ADF_4XXX_MAX_ACCELERATORS;
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hw_data->num_engines = ADF_4XXX_MAX_ACCELENGINES;
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hw_data->num_logical_accel = 1;
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hw_data->tx_rx_gap = ADF_4XXX_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_4XXX_TX_RINGS_MASK;
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hw_data->alloc_irq = adf_isr_resource_alloc;
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hw_data->free_irq = adf_isr_resource_free;
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hw_data->enable_error_correction = adf_enable_error_correction;
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hw_data->get_accel_mask = get_accel_mask;
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hw_data->get_ae_mask = get_ae_mask;
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hw_data->get_num_accels = get_num_accels;
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hw_data->get_num_aes = get_num_aes;
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hw_data->get_sram_bar_id = get_sram_bar_id;
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hw_data->get_etr_bar_id = get_etr_bar_id;
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hw_data->get_misc_bar_id = get_misc_bar_id;
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hw_data->get_arb_info = get_arb_info;
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hw_data->get_admin_info = get_admin_info;
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hw_data->get_accel_cap = get_accel_cap;
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hw_data->get_sku = get_sku;
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hw_data->fw_name = ADF_4XXX_FW;
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hw_data->fw_mmp_name = ADF_4XXX_MMP;
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hw_data->init_admin_comms = adf_init_admin_comms;
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hw_data->exit_admin_comms = adf_exit_admin_comms;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->send_admin_init = adf_send_admin_init;
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hw_data->init_arb = adf_init_arb;
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hw_data->exit_arb = adf_exit_arb;
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hw_data->get_arb_mapping = adf_get_arbiter_mapping;
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hw_data->enable_ints = adf_enable_ints;
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hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms;
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hw_data->reset_device = adf_reset_flr;
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hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;
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hw_data->admin_ae_mask = ADF_4XXX_ADMIN_AE_MASK;
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hw_data->uof_get_num_objs = uof_get_num_objs;
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hw_data->uof_get_name = uof_get_name;
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hw_data->uof_get_ae_mask = uof_get_ae_mask;
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hw_data->set_msix_rttable = set_msix_default_rttable;
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hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
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adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);
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}
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void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class->instances--;
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}
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