2572f00db8
This adds support for the Microchip PIC32 MIPS microcontroller with the specific variant PIC32MZDA. PIC32MZDA is based on the MIPS m14KEc core and boots using device tree. This includes an early pin setup and early clock setup needed prior to device tree being initialized. In additon, an interface is provided to synchronize access to registers shared across several peripherals. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12097/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/*
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* Joshua Henderson <joshua.henderson@microchip.com>
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* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef _ASM_MACH_PIC32_H
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#define _ASM_MACH_PIC32_H
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#include <linux/io.h>
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/*
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* PIC32 register offsets for SET/CLR/INV where supported.
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*/
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#define PIC32_CLR(_reg) ((_reg) + 0x04)
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#define PIC32_SET(_reg) ((_reg) + 0x08)
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#define PIC32_INV(_reg) ((_reg) + 0x0C)
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/*
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* PIC32 Base Register Offsets
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*/
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#define PIC32_BASE_CONFIG 0x1f800000
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#define PIC32_BASE_OSC 0x1f801200
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#define PIC32_BASE_RESET 0x1f801240
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#define PIC32_BASE_PPS 0x1f801400
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#define PIC32_BASE_UART 0x1f822000
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#define PIC32_BASE_PORT 0x1f860000
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#define PIC32_BASE_DEVCFG2 0x1fc4ff44
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/*
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* Register unlock sequence required for some register access.
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*/
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void pic32_syskey_unlock_debug(const char *fn, const ulong ln);
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#define pic32_syskey_unlock() \
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pic32_syskey_unlock_debug(__func__, __LINE__)
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#endif /* _ASM_MACH_PIC32_H */
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