60bf0a3984
Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> [conor: squashed in the removal of the S7's non-existent mmu] Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>