dd08ebf6c3
Xe, is a new driver for Intel GPUs that supports both integrated and discrete platforms starting with Tiger Lake (first Intel Xe Architecture). The code is at a stage where it is already functional and has experimental support for multiple platforms starting from Tiger Lake, with initial support implemented in Mesa (for Iris and Anv, our OpenGL and Vulkan drivers), as well as in NEO (for OpenCL and Level0). The new Xe driver leverages a lot from i915. As for display, the intent is to share the display code with the i915 driver so that there is maximum reuse there. But it is not added in this patch. This initial work is a collaboration of many people and unfortunately the big squashed patch won't fully honor the proper credits. But let's get some git quick stats so we can at least try to preserve some of the credits: Co-developed-by: Matthew Brost <matthew.brost@intel.com> Co-developed-by: Matthew Auld <matthew.auld@intel.com> Co-developed-by: Matt Roper <matthew.d.roper@intel.com> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Co-developed-by: Francois Dugast <francois.dugast@intel.com> Co-developed-by: Lucas De Marchi <lucas.demarchi@intel.com> Co-developed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Co-developed-by: Philippe Lecluse <philippe.lecluse@intel.com> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> Co-developed-by: Jani Nikula <jani.nikula@intel.com> Co-developed-by: José Roberto de Souza <jose.souza@intel.com> Co-developed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Co-developed-by: Dave Airlie <airlied@redhat.com> Co-developed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Co-developed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Co-developed-by: Mauro Carvalho Chehab <mchehab@kernel.org> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
50 lines
1.9 KiB
C
50 lines
1.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2014-2021 Intel Corporation
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*/
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#ifndef _ABI_GUC_COMMUNICATION_MMIO_ABI_H
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#define _ABI_GUC_COMMUNICATION_MMIO_ABI_H
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/**
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* DOC: GuC MMIO based communication
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*
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* The MMIO based communication between Host and GuC relies on special
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* hardware registers which format could be defined by the software
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* (so called scratch registers).
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*
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* Each MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H)
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* messages, which maximum length depends on number of available scratch
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* registers, is directly written into those scratch registers.
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*
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* For Gen9+, there are 16 software scratch registers 0xC180-0xC1B8,
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* but no H2G command takes more than 4 parameters and the GuC firmware
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* itself uses an 4-element array to store the H2G message.
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*
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* For Gen11+, there are additional 4 registers 0x190240-0x19024C, which
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* are, regardless on lower count, preferred over legacy ones.
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*
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* The MMIO based communication is mainly used during driver initialization
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* phase to setup the `CTB based communication`_ that will be used afterwards.
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*/
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#define GUC_MAX_MMIO_MSG_LEN 4
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/**
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* DOC: MMIO HXG Message
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*
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* Format of the MMIO messages follows definitions of `HXG Message`_.
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*
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* +---+-------+--------------------------------------------------------------+
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* | | Bits | Description |
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* +===+=======+==============================================================+
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* | 0 | 31:0 | |
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* +---+-------+ |
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* |...| | [Embedded `HXG Message`_] |
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* +---+-------+ |
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* | n | 31:0 | |
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* +---+-------+--------------------------------------------------------------+
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*/
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#endif
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