92d44a422d
Expose the card reactive critical (I1) power. I1 is exposed as power1_crit in microwatts (typically for client products) or as curr1_crit in milliamperes (typically for server). v2: Move PCODE_MBOX macro to pcode file (Riana) v3: s/IS_DG2/(gt_to_xe(gt)->info.platform == XE_DG2) v4: Fix review comments (Andi) Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/20230925081842.3566834-3-badal.nilawar@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
50 lines
1.4 KiB
C
50 lines
1.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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/* Internal to xe_pcode */
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#include "regs/xe_reg_defs.h"
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#define PCODE_MAILBOX XE_REG(0x138124)
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#define PCODE_READY REG_BIT(31)
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#define PCODE_MB_PARAM2 REG_GENMASK(23, 16)
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#define PCODE_MB_PARAM1 REG_GENMASK(15, 8)
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#define PCODE_MB_COMMAND REG_GENMASK(7, 0)
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#define PCODE_ERROR_MASK 0xFF
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#define PCODE_SUCCESS 0x0
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#define PCODE_ILLEGAL_CMD 0x1
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#define PCODE_TIMEOUT 0x2
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#define PCODE_ILLEGAL_DATA 0x3
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#define PCODE_ILLEGAL_SUBCOMMAND 0x4
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#define PCODE_LOCKED 0x6
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#define PCODE_GT_RATIO_OUT_OF_RANGE 0x10
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#define PCODE_REJECTED 0x11
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#define PCODE_DATA0 XE_REG(0x138128)
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#define PCODE_DATA1 XE_REG(0x13812C)
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/* Min Freq QOS Table */
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#define PCODE_WRITE_MIN_FREQ_TABLE 0x8
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#define PCODE_READ_MIN_FREQ_TABLE 0x9
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#define PCODE_FREQ_RING_RATIO_SHIFT 16
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/* PCODE Init */
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#define DGFX_PCODE_STATUS 0x7E
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#define DGFX_GET_INIT_STATUS 0x0
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#define DGFX_INIT_STATUS_COMPLETE 0x1
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#define PCODE_POWER_SETUP 0x7C
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#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
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#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
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#define POWER_SETUP_I1_WATTS REG_BIT(31)
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#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
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#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
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struct pcode_err_decode {
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int errno;
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const char *str;
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};
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