ad8e5c2d77
MISR support is the debug feature present in Snapdragon chipsets. At the layer mixer and interfaces, MISR algorithm can generate CRC signatures of the pixel data which can be used for validating the frames generated. Since there are no clients for this feature, strip down the support from the driver. changes in v4: - changed introduced in the series changes in v5: - update commit text with the need for the change(Sean) Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
122 lines
3.3 KiB
C
122 lines
3.3 KiB
C
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DPU_HW_INTF_H
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#define _DPU_HW_INTF_H
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_util.h"
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#include "dpu_hw_blk.h"
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struct dpu_hw_intf;
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/* intf timing settings */
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struct intf_timing_params {
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u32 width; /* active width */
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u32 height; /* active height */
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u32 xres; /* Display panel width */
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u32 yres; /* Display panel height */
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u32 h_back_porch;
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u32 h_front_porch;
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u32 v_back_porch;
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u32 v_front_porch;
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u32 hsync_pulse_width;
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u32 vsync_pulse_width;
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u32 hsync_polarity;
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u32 vsync_polarity;
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u32 border_clr;
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u32 underflow_clr;
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u32 hsync_skew;
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};
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struct intf_prog_fetch {
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u8 enable;
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/* vsync counter for the front porch pixel line */
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u32 fetch_start;
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};
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struct intf_status {
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u8 is_en; /* interface timing engine is enabled or not */
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u32 frame_count; /* frame count since timing engine enabled */
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u32 line_count; /* current line count including blanking */
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};
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/**
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* struct dpu_hw_intf_ops : Interface to the interface Hw driver functions
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* Assumption is these functions will be called after clocks are enabled
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* @ setup_timing_gen : programs the timing engine
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* @ setup_prog_fetch : enables/disables the programmable fetch logic
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* @ enable_timing: enable/disable timing engine
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* @ get_status: returns if timing engine is enabled or not
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* @ get_line_count: reads current vertical line counter
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*/
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struct dpu_hw_intf_ops {
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void (*setup_timing_gen)(struct dpu_hw_intf *intf,
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const struct intf_timing_params *p,
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const struct dpu_format *fmt);
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void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
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const struct intf_prog_fetch *fetch);
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void (*enable_timing)(struct dpu_hw_intf *intf,
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u8 enable);
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void (*get_status)(struct dpu_hw_intf *intf,
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struct intf_status *status);
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u32 (*get_line_count)(struct dpu_hw_intf *intf);
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};
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struct dpu_hw_intf {
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struct dpu_hw_blk base;
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struct dpu_hw_blk_reg_map hw;
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/* intf */
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enum dpu_intf idx;
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const struct dpu_intf_cfg *cap;
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const struct dpu_mdss_cfg *mdss;
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/* ops */
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struct dpu_hw_intf_ops ops;
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};
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/**
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* to_dpu_hw_intf - convert base object dpu_hw_base to container
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* @hw: Pointer to base hardware block
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* return: Pointer to hardware block container
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*/
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static inline struct dpu_hw_intf *to_dpu_hw_intf(struct dpu_hw_blk *hw)
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{
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return container_of(hw, struct dpu_hw_intf, base);
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}
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/**
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* dpu_hw_intf_init(): Initializes the intf driver for the passed
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* interface idx.
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* @idx: interface index for which driver object is required
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* @addr: mapped register io address of MDP
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* @m : pointer to mdss catalog data
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*/
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struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
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void __iomem *addr,
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struct dpu_mdss_cfg *m);
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/**
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* dpu_hw_intf_destroy(): Destroys INTF driver context
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* @intf: Pointer to INTF driver context
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*/
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void dpu_hw_intf_destroy(struct dpu_hw_intf *intf);
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#endif /*_DPU_HW_INTF_H */
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