SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end composition engine. It blends video and graphic images stored in the frame buffers and scans out the composed image to a display sink (over DSI/DP). The following diagram represents hardware blocks for a simple pipeline (two planes are present on a given crtc which is connected to a DSI connector): MDSS +---------------------------------+ | +-----------------------------+ | | | DPU | | | | +--------+ +--------+ | | | | | SSPP | | SSPP | | | | | +----+---+ +----+---+ | | | | | | | | | | +----v-----------v---+ | | | | | Layer Mixer (LM) | | | | | +--------------------+ | | | | +--------------------+ | | | | | PingPong (PP) | | | | | +--------------------+ | | | | +--------------------+ | | | | | INTERFACE (VIDEO) | | | | | +---+----------------+ | | | +------|----------------------+ | | | | | +------|---------------------+ | | | | DISPLAY PERIPHERALS | | | | +---v-+ +-----+ | | | | | DSI | | DP | | | | | +-----+ +-----+ | | | +----------------------------+ | +---------------------------------+ The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs) depends on SoC capabilities. Overview of DPU sub-blocks: --------------------------- * Source Surface Processor (SSPP): Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are capable of performing format conversion, scaling and quality improvement for source surfaces. * Layer Mixer (LM): Blend source surfaces together (in requested zorder) * PingPong (PP): This block controls frame done interrupt output, EOL and EOF generation, overflow/underflow control. * Display interface (INTF): Timing generator and interface connecting the display peripherals. DRM components mapping to DPU architecture: ------------------------------------------ PLANEs maps to SSPPs CRTC maps to LMs Encoder maps to PPs, INTFs Data flow setup: --------------- MDSS hardware can support various data flows (e.g.): - Dual pipe: Output from two LMs combined to single display. - Split display: Output from two LMs connected to two separate interfaces. The hardware capabilities determine the number of concurrent data paths possible. Any control path (i.e. pipeline w/i DPU) can be routed to any of the hardware data paths. A given control path can be triggered, flushed and controlled independently. Changes in v3: - Move msm_media_info.h from uapi to dpu/ subdir - Remove preclose callback dpu (it's handled in core) - Fix kbuild warnings with parent_ops - Remove unused functions from dpu_core_irq - Rename mdss_phys to mdss - Rename mdp_phys address space to mdp - Drop _phys from vbif and regdma binding names Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> [robclark minor rebase] Signed-off-by: Rob Clark <robdclark@gmail.com>
137 lines
3.9 KiB
C
137 lines
3.9 KiB
C
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DPU_HW_PINGPONG_H
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#define _DPU_HW_PINGPONG_H
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_util.h"
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#include "dpu_hw_blk.h"
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struct dpu_hw_pingpong;
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struct dpu_hw_tear_check {
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/*
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* This is ratio of MDP VSYNC clk freq(Hz) to
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* refresh rate divided by no of lines
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*/
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u32 vsync_count;
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u32 sync_cfg_height;
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u32 vsync_init_val;
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u32 sync_threshold_start;
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u32 sync_threshold_continue;
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u32 start_pos;
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u32 rd_ptr_irq;
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u8 hw_vsync_mode;
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};
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struct dpu_hw_pp_vsync_info {
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u32 rd_ptr_init_val; /* value of rd pointer at vsync edge */
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u32 rd_ptr_frame_count; /* num frames sent since enabling interface */
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u32 rd_ptr_line_count; /* current line on panel (rd ptr) */
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u32 wr_ptr_line_count; /* current line within pp fifo (wr ptr) */
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};
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/**
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*
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* struct dpu_hw_pingpong_ops : Interface to the pingpong Hw driver functions
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* Assumption is these functions will be called after clocks are enabled
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* @setup_tearcheck : program tear check values
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* @enable_tearcheck : enables tear check
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* @get_vsync_info : retries timing info of the panel
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* @setup_dither : function to program the dither hw block
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* @get_line_count: obtain current vertical line counter
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*/
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struct dpu_hw_pingpong_ops {
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/**
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* enables vysnc generation and sets up init value of
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* read pointer and programs the tear check cofiguration
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*/
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int (*setup_tearcheck)(struct dpu_hw_pingpong *pp,
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struct dpu_hw_tear_check *cfg);
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/**
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* enables tear check block
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*/
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int (*enable_tearcheck)(struct dpu_hw_pingpong *pp,
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bool enable);
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/**
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* read, modify, write to either set or clear listening to external TE
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* @Return: 1 if TE was originally connected, 0 if not, or -ERROR
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*/
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int (*connect_external_te)(struct dpu_hw_pingpong *pp,
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bool enable_external_te);
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/**
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* provides the programmed and current
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* line_count
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*/
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int (*get_vsync_info)(struct dpu_hw_pingpong *pp,
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struct dpu_hw_pp_vsync_info *info);
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/**
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* poll until write pointer transmission starts
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* @Return: 0 on success, -ETIMEDOUT on timeout
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*/
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int (*poll_timeout_wr_ptr)(struct dpu_hw_pingpong *pp, u32 timeout_us);
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/**
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* Obtain current vertical line counter
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*/
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u32 (*get_line_count)(struct dpu_hw_pingpong *pp);
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};
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struct dpu_hw_pingpong {
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struct dpu_hw_blk base;
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struct dpu_hw_blk_reg_map hw;
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/* pingpong */
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enum dpu_pingpong idx;
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const struct dpu_pingpong_cfg *caps;
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/* ops */
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struct dpu_hw_pingpong_ops ops;
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};
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/**
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* dpu_hw_pingpong - convert base object dpu_hw_base to container
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* @hw: Pointer to base hardware block
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* return: Pointer to hardware block container
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*/
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static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw)
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{
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return container_of(hw, struct dpu_hw_pingpong, base);
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}
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/**
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* dpu_hw_pingpong_init - initializes the pingpong driver for the passed
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* pingpong idx.
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* @idx: Pingpong index for which driver object is required
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* @addr: Mapped register io address of MDP
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* @m: Pointer to mdss catalog data
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* Returns: Error code or allocated dpu_hw_pingpong context
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*/
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struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
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void __iomem *addr,
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struct dpu_mdss_cfg *m);
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/**
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* dpu_hw_pingpong_destroy - destroys pingpong driver context
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* should be called to free the context
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* @pp: Pointer to PP driver context returned by dpu_hw_pingpong_init
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*/
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void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp);
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#endif /*_DPU_HW_PINGPONG_H */
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