6a2f0b2d3b
Add a DT description of the CPU and cache hierarchy as found on the AMD Seattle SOC. Given the tight coupling of the PMU with the CPUs, move the PMU node into the cpu .dtsi file as well, and add the missing affinity description. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
225 lines
4.0 KiB
Plaintext
225 lines
4.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/ {
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cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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};
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cluster3 {
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core0 {
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cpu = <&CPU6>;
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};
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core1 {
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cpu = <&CPU7>;
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};
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};
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0>;
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_0>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1>;
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_0>;
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};
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x100>;
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_1>;
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x101>;
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_1>;
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};
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CPU4: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x200>;
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_2>;
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};
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CPU5: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x201>;
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_2>;
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};
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CPU6: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x300>;
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_3>;
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};
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CPU7: cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x301>;
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_3>;
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};
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};
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L2_0: l2-cache0 {
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-unified;
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next-level-cache = <&L3>;
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};
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L2_1: l2-cache1 {
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-unified;
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next-level-cache = <&L3>;
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};
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L2_2: l2-cache2 {
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-unified;
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next-level-cache = <&L3>;
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};
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L2_3: l2-cache3 {
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-unified;
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next-level-cache = <&L3>;
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};
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L3: l3-cache {
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cache-level = <3>;
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cache-size = <0x800000>;
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cache-line-size = <64>;
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cache-sets = <8192>;
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cache-unified;
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};
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pmu {
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compatible = "arm,cortex-a57-pmu";
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interrupts = <0x0 0x7 0x4>,
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<0x0 0x8 0x4>,
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<0x0 0x9 0x4>,
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<0x0 0xa 0x4>,
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<0x0 0xb 0x4>,
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<0x0 0xc 0x4>,
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<0x0 0xd 0x4>,
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<0x0 0xe 0x4>;
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interrupt-affinity = <&CPU0>,
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<&CPU1>,
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<&CPU2>,
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<&CPU3>,
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<&CPU4>,
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<&CPU5>,
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<&CPU6>,
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<&CPU7>;
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};
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};
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