6cc82f07fc
This adds initial device tree support for the Nuvoton NPCM845 Board Management controller (BMC) SoC family. The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and have various peripheral IPs. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
77 lines
1.7 KiB
Plaintext
77 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
|
|
|
|
#include "nuvoton-common-npcm8xx.dtsi"
|
|
|
|
/ {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a35";
|
|
clocks = <&clk NPCM8XX_CLK_CPU>;
|
|
reg = <0x0 0x0>;
|
|
next-level-cache = <&l2>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a35";
|
|
clocks = <&clk NPCM8XX_CLK_CPU>;
|
|
reg = <0x0 0x1>;
|
|
next-level-cache = <&l2>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a35";
|
|
clocks = <&clk NPCM8XX_CLK_CPU>;
|
|
reg = <0x0 0x2>;
|
|
next-level-cache = <&l2>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a35";
|
|
clocks = <&clk NPCM8XX_CLK_CPU>;
|
|
reg = <0x0 0x3>;
|
|
next-level-cache = <&l2>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
l2: l2-cache {
|
|
compatible = "cache";
|
|
};
|
|
};
|
|
|
|
arm-pmu {
|
|
compatible = "arm,cortex-a35-pmu";
|
|
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|