65c9ad77cb
Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
92 lines
2.5 KiB
C
92 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Chen Zhong <chen.zhong@mediatek.com>
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* Sean Wang <sean.wang@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt7622-clk.h>
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#define GATE_ETH(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
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static const struct mtk_gate_regs eth_cg_regs = {
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.set_ofs = 0x30,
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.clr_ofs = 0x30,
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.sta_ofs = 0x30,
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};
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static const struct mtk_gate eth_clks[] = {
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GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
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GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
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GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
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GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
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GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
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};
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static const struct mtk_gate_regs sgmii_cg_regs = {
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.set_ofs = 0xE4,
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.clr_ofs = 0xE4,
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.sta_ofs = 0xE4,
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};
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#define GATE_SGMII(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
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static const struct mtk_gate sgmii_clks[] = {
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GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
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"ssusb_tx250m", 2),
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GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
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"ssusb_eq_rx250m", 3),
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GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
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"ssusb_cdr_ref", 4),
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GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
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"ssusb_cdr_fb", 5),
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};
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static u16 rst_ofs[] = { 0x34, };
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static const struct mtk_clk_rst_desc clk_rst_desc = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(rst_ofs),
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};
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static const struct mtk_clk_desc eth_desc = {
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.clks = eth_clks,
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.num_clks = ARRAY_SIZE(eth_clks),
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.rst_desc = &clk_rst_desc,
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};
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static const struct mtk_clk_desc sgmii_desc = {
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.clks = sgmii_clks,
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.num_clks = ARRAY_SIZE(sgmii_clks),
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};
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static const struct of_device_id of_match_clk_mt7622_eth[] = {
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{ .compatible = "mediatek,mt7622-ethsys", .data = ð_desc },
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{ .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_eth);
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static struct platform_driver clk_mt7622_eth_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt7622-eth",
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.of_match_table = of_match_clk_mt7622_eth,
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},
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};
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module_platform_driver(clk_mt7622_eth_drv);
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MODULE_LICENSE("GPL");
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