620565a76b
Finish the final part of the job, once again updating some names to match the current spec. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
198 lines
5.1 KiB
C
198 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* IOMMU API for ARM architected SMMU implementations.
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*
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* Copyright (C) 2013 ARM Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#ifndef _ARM_SMMU_REGS_H
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#define _ARM_SMMU_REGS_H
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#include <linux/bits.h>
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/* Configuration registers */
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#define ARM_SMMU_GR0_sCR0 0x0
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#define sCR0_VMID16EN BIT(31)
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#define sCR0_BSU GENMASK(15, 14)
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#define sCR0_FB BIT(13)
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#define sCR0_PTM BIT(12)
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#define sCR0_VMIDPNE BIT(11)
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#define sCR0_USFCFG BIT(10)
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#define sCR0_GCFGFIE BIT(5)
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#define sCR0_GCFGFRE BIT(4)
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#define sCR0_EXIDENABLE BIT(3)
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#define sCR0_GFIE BIT(2)
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#define sCR0_GFRE BIT(1)
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#define sCR0_CLIENTPD BIT(0)
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/* Auxiliary Configuration register */
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#define ARM_SMMU_GR0_sACR 0x10
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/* Identification registers */
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#define ARM_SMMU_GR0_ID0 0x20
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#define ID0_S1TS BIT(30)
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#define ID0_S2TS BIT(29)
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#define ID0_NTS BIT(28)
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#define ID0_SMS BIT(27)
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#define ID0_ATOSNS BIT(26)
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#define ID0_PTFS_NO_AARCH32 BIT(25)
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#define ID0_PTFS_NO_AARCH32S BIT(24)
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#define ID0_NUMIRPT GENMASK(23, 16)
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#define ID0_CTTW BIT(14)
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#define ID0_NUMSIDB GENMASK(12, 9)
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#define ID0_EXIDS BIT(8)
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#define ID0_NUMSMRG GENMASK(7, 0)
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#define ARM_SMMU_GR0_ID1 0x24
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#define ID1_PAGESIZE BIT(31)
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#define ID1_NUMPAGENDXB GENMASK(30, 28)
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#define ID1_NUMS2CB GENMASK(23, 16)
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#define ID1_NUMCB GENMASK(7, 0)
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#define ARM_SMMU_GR0_ID2 0x28
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#define ID2_VMID16 BIT(15)
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#define ID2_PTFS_64K BIT(14)
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#define ID2_PTFS_16K BIT(13)
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#define ID2_PTFS_4K BIT(12)
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#define ID2_UBS GENMASK(11, 8)
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#define ID2_OAS GENMASK(7, 4)
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#define ID2_IAS GENMASK(3, 0)
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#define ARM_SMMU_GR0_ID3 0x2c
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#define ARM_SMMU_GR0_ID4 0x30
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#define ARM_SMMU_GR0_ID5 0x34
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#define ARM_SMMU_GR0_ID6 0x38
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#define ARM_SMMU_GR0_ID7 0x3c
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#define ID7_MAJOR GENMASK(7, 4)
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#define ID7_MINOR GENMASK(3, 0)
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#define ARM_SMMU_GR0_sGFSR 0x48
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#define ARM_SMMU_GR0_sGFSYNR0 0x50
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#define ARM_SMMU_GR0_sGFSYNR1 0x54
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#define ARM_SMMU_GR0_sGFSYNR2 0x58
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/* Global TLB invalidation */
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#define ARM_SMMU_GR0_TLBIVMID 0x64
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#define ARM_SMMU_GR0_TLBIALLNSNH 0x68
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#define ARM_SMMU_GR0_TLBIALLH 0x6c
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#define ARM_SMMU_GR0_sTLBGSYNC 0x70
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#define ARM_SMMU_GR0_sTLBGSTATUS 0x74
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#define sTLBGSTATUS_GSACTIVE BIT(0)
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/* Stream mapping registers */
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#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
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#define SMR_VALID BIT(31)
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#define SMR_MASK GENMASK(31, 16)
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#define SMR_ID GENMASK(15, 0)
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#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
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#define S2CR_PRIVCFG GENMASK(25, 24)
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enum arm_smmu_s2cr_privcfg {
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S2CR_PRIVCFG_DEFAULT,
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S2CR_PRIVCFG_DIPAN,
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S2CR_PRIVCFG_UNPRIV,
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S2CR_PRIVCFG_PRIV,
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};
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#define S2CR_TYPE GENMASK(17, 16)
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enum arm_smmu_s2cr_type {
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S2CR_TYPE_TRANS,
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S2CR_TYPE_BYPASS,
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S2CR_TYPE_FAULT,
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};
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#define S2CR_EXIDVALID BIT(10)
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#define S2CR_CBNDX GENMASK(7, 0)
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/* Context bank attribute registers */
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#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
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#define CBAR_IRPTNDX GENMASK(31, 24)
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#define CBAR_TYPE GENMASK(17, 16)
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enum arm_smmu_cbar_type {
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CBAR_TYPE_S2_TRANS,
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CBAR_TYPE_S1_TRANS_S2_BYPASS,
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CBAR_TYPE_S1_TRANS_S2_FAULT,
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CBAR_TYPE_S1_TRANS_S2_TRANS,
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};
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#define CBAR_S1_MEMATTR GENMASK(15, 12)
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#define CBAR_S1_MEMATTR_WB 0xf
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#define CBAR_S1_BPSHCFG GENMASK(9, 8)
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#define CBAR_S1_BPSHCFG_NSH 3
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#define CBAR_VMID GENMASK(7, 0)
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#define ARM_SMMU_GR1_CBFRSYNRA(n) (0x400 + ((n) << 2))
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#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
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#define CBA2R_VMID16 GENMASK(31, 16)
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#define CBA2R_VA64 BIT(0)
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#define ARM_SMMU_CB_SCTLR 0x0
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#define SCTLR_S1_ASIDPNE BIT(12)
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#define SCTLR_CFCFG BIT(7)
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#define SCTLR_CFIE BIT(6)
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#define SCTLR_CFRE BIT(5)
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#define SCTLR_E BIT(4)
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#define SCTLR_AFE BIT(2)
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#define SCTLR_TRE BIT(1)
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#define SCTLR_M BIT(0)
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#define ARM_SMMU_CB_ACTLR 0x4
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#define ARM_SMMU_CB_RESUME 0x8
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#define RESUME_TERMINATE BIT(0)
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#define ARM_SMMU_CB_TCR2 0x10
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#define TCR2_SEP GENMASK(17, 15)
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#define TCR2_SEP_UPSTREAM 0x7
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#define TCR2_AS BIT(4)
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#define ARM_SMMU_CB_TTBR0 0x20
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#define ARM_SMMU_CB_TTBR1 0x28
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#define TTBRn_ASID GENMASK_ULL(63, 48)
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#define ARM_SMMU_CB_TCR 0x30
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#define ARM_SMMU_CB_CONTEXTIDR 0x34
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#define ARM_SMMU_CB_S1_MAIR0 0x38
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#define ARM_SMMU_CB_S1_MAIR1 0x3c
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#define ARM_SMMU_CB_PAR 0x50
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#define CB_PAR_F BIT(0)
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#define ARM_SMMU_CB_FSR 0x58
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#define FSR_MULTI BIT(31)
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#define FSR_SS BIT(30)
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#define FSR_UUT BIT(8)
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#define FSR_ASF BIT(7)
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#define FSR_TLBLKF BIT(6)
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#define FSR_TLBMCF BIT(5)
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#define FSR_EF BIT(4)
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#define FSR_PF BIT(3)
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#define FSR_AFF BIT(2)
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#define FSR_TF BIT(1)
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#define FSR_IGN (FSR_AFF | FSR_ASF | \
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FSR_TLBMCF | FSR_TLBLKF)
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#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
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FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
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#define ARM_SMMU_CB_FAR 0x60
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#define ARM_SMMU_CB_FSYNR0 0x68
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#define FSYNR0_WNR BIT(4)
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#define ARM_SMMU_CB_S1_TLBIVA 0x600
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#define ARM_SMMU_CB_S1_TLBIASID 0x610
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#define ARM_SMMU_CB_S1_TLBIVAL 0x620
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#define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
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#define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
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#define ARM_SMMU_CB_TLBSYNC 0x7f0
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#define ARM_SMMU_CB_TLBSTATUS 0x7f4
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#define ARM_SMMU_CB_ATS1PR 0x800
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#define ARM_SMMU_CB_ATSR 0x8f0
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#define ATSR_ACTIVE BIT(0)
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#endif /* _ARM_SMMU_REGS_H */
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