cf6e26c71b
We had read/write function for Codec, Platform, etc,
but these has been merged into snd_soc_component_read/write().
Internally, it is using regmap or driver function.
In read case, each styles are like below
regmap
ret = regmap_read(..., reg, &val);
driver function
val = xxx->read(..., reg);
Because of this kind of different style, to keep same read style,
when we merged each read function into snd_soc_component_read(),
we created snd_soc_component_read32(), like below.
commit 738b49efe6
("ASoC: add snd_soc_component_read32")
(1) val = snd_soc_component_read32(component, reg);
(2) ret = snd_soc_component_read(component, reg, &val);
Many drivers are using snd_soc_component_read32(), and
some drivers are using snd_soc_component_read() today.
In generally, we don't check read function successes,
because, we will have many other issues at initial timing
if read function didn't work.
Now we can use soc_component_err() when error case.
This means, it is easy to notice if error occurred.
This patch aggressively merge snd_soc_component_read() and _read32(),
and makes snd_soc_component_read/write() as generally style.
This patch do
1) merge snd_soc_component_read() and snd_soc_component_read32()
2) it uses soc_component_err() when error case (easy to notice)
3) keeps read32 for now by #define
4) update snd_soc_component_read() for all drivers
Because _read() user drivers are not too many, this patch changes
all user drivers.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Link: https://lore.kernel.org/r/87sgev4mfl.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
153 lines
3.8 KiB
C
153 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2020 BayLibre, SAS.
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// Author: Jerome Brunet <jbrunet@baylibre.com>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "aiu.h"
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#include "aiu-fifo.h"
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#define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
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#define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
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#define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
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#define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11)
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#define AIU_MEM_I2S_MASKS_IRQ_BLOCK GENMASK(31, 16)
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#define AIU_MEM_I2S_CONTROL_MODE_16BIT BIT(6)
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#define AIU_MEM_I2S_BUF_CNTL_INIT BIT(0)
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#define AIU_RST_SOFT_I2S_FAST BIT(0)
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#define AIU_FIFO_I2S_BLOCK 256
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static struct snd_pcm_hardware fifo_i2s_pcm = {
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.info = (SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_PAUSE),
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.formats = AIU_FORMATS,
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.rate_min = 5512,
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.rate_max = 192000,
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.channels_min = 2,
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.channels_max = 8,
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.period_bytes_min = AIU_FIFO_I2S_BLOCK,
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.period_bytes_max = AIU_FIFO_I2S_BLOCK * USHRT_MAX,
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.periods_min = 2,
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.periods_max = UINT_MAX,
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/* No real justification for this */
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.buffer_bytes_max = 1 * 1024 * 1024,
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};
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static int aiu_fifo_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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snd_soc_component_write(component, AIU_RST_SOFT,
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AIU_RST_SOFT_I2S_FAST);
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snd_soc_component_read(component, AIU_I2S_SYNC);
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break;
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}
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return aiu_fifo_trigger(substream, cmd, dai);
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}
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static int aiu_fifo_i2s_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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int ret;
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ret = aiu_fifo_prepare(substream, dai);
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if (ret)
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return ret;
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snd_soc_component_update_bits(component,
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AIU_MEM_I2S_BUF_CNTL,
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AIU_MEM_I2S_BUF_CNTL_INIT,
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AIU_MEM_I2S_BUF_CNTL_INIT);
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snd_soc_component_update_bits(component,
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AIU_MEM_I2S_BUF_CNTL,
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AIU_MEM_I2S_BUF_CNTL_INIT, 0);
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return 0;
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}
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static int aiu_fifo_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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struct aiu_fifo *fifo = dai->playback_dma_data;
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unsigned int val;
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int ret;
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ret = aiu_fifo_hw_params(substream, params, dai);
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if (ret)
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return ret;
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switch (params_physical_width(params)) {
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case 16:
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val = AIU_MEM_I2S_CONTROL_MODE_16BIT;
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break;
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case 32:
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val = 0;
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break;
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default:
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dev_err(dai->dev, "Unsupported physical width %u\n",
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params_physical_width(params));
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return -EINVAL;
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}
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snd_soc_component_update_bits(component, AIU_MEM_I2S_CONTROL,
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AIU_MEM_I2S_CONTROL_MODE_16BIT,
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val);
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/* Setup the irq periodicity */
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val = params_period_bytes(params) / fifo->fifo_block;
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val = FIELD_PREP(AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
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snd_soc_component_update_bits(component, AIU_MEM_I2S_MASKS,
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AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
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return 0;
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}
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const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops = {
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.trigger = aiu_fifo_i2s_trigger,
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.prepare = aiu_fifo_i2s_prepare,
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.hw_params = aiu_fifo_i2s_hw_params,
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.hw_free = aiu_fifo_hw_free,
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.startup = aiu_fifo_startup,
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.shutdown = aiu_fifo_shutdown,
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};
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int aiu_fifo_i2s_dai_probe(struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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struct aiu *aiu = snd_soc_component_get_drvdata(component);
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struct aiu_fifo *fifo;
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int ret;
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ret = aiu_fifo_dai_probe(dai);
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if (ret)
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return ret;
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fifo = dai->playback_dma_data;
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fifo->pcm = &fifo_i2s_pcm;
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fifo->mem_offset = AIU_MEM_I2S_START;
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fifo->fifo_block = AIU_FIFO_I2S_BLOCK;
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fifo->pclk = aiu->i2s.clks[PCLK].clk;
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fifo->irq = aiu->i2s.irq;
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return 0;
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}
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