9ff9139b5d
When the driver starts the device, it enables all the necessary interrupts. However interrupts associated to host rings are enabled by default on all GEN2 devices (except for dh895x) even when SR-IOV is active. Fix this behaviour by checking if data structures associated to VFs have been allocated to determine whether to enable such interrupts or not. Since the logic for the fix is the same across GEN2 devices, replace the function to be fixed (adf_enable_ints()) with a single one (adf_gen2_enable_ints()) in the common GEN2 code in adf_gen2_hw_data.c. Likewise, remove the unnecessary duplication of defines too. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
29 lines
918 B
C
29 lines
918 B
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#ifndef ADF_C62X_HW_DATA_H_
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#define ADF_C62X_HW_DATA_H_
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/* PCIe configuration space */
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#define ADF_C62X_SRAM_BAR 0
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#define ADF_C62X_PMISC_BAR 1
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#define ADF_C62X_ETR_BAR 2
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#define ADF_C62X_MAX_ACCELERATORS 5
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#define ADF_C62X_MAX_ACCELENGINES 10
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#define ADF_C62X_ACCELERATORS_REG_OFFSET 16
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#define ADF_C62X_ACCELERATORS_MASK 0x1F
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#define ADF_C62X_ACCELENGINES_MASK 0x3FF
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#define ADF_C62X_ETR_MAX_BANKS 16
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#define ADF_C62X_SOFTSTRAP_CSR_OFFSET 0x2EC
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/* AE to function mapping */
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#define ADF_C62X_AE2FUNC_MAP_GRP_A_NUM_REGS 80
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#define ADF_C62X_AE2FUNC_MAP_GRP_B_NUM_REGS 10
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/* Firmware Binary */
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#define ADF_C62X_FW "qat_c62x.bin"
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#define ADF_C62X_MMP "qat_c62x_mmp.bin"
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void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data);
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void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data);
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#endif
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