Add the pmc gpio node to the device tree. Versal devices are the industry's first adaptive compute acceleration platforms. https://www.xilinx.com/support/documentation/data_sheets/ds950-versal-overview.pdf On the Versal platform, we are using two customized GPIO controllers(IP) which were used in Zynq/ZynqMp platform. One of them present in the Platform Management Controller(PMC) block and other in Processing System(PS) block. In PMC_GPIO only Bank0,1,3 & 4 are enabled and in PS_GPIO only Bank 0 & 3 are enabled. You can find more details of GPIO IP in ZynqMP TRM General Purpose I/O(Chapter-27). https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
37 lines
1.3 KiB
Plaintext
37 lines
1.3 KiB
Plaintext
Xilinx Zynq GPIO controller Device Tree Bindings
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Required properties:
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- #gpio-cells : Should be two
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- First cell is the GPIO line number
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- Second cell is used to specify optional
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parameters (unused)
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- compatible : Should be "xlnx,zynq-gpio-1.0" or
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"xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
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or "xlnx,pmc-gpio-1.0
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- clocks : Clock specifier (see clock bindings for details)
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- gpio-controller : Marks the device node as a GPIO controller.
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- interrupts : Interrupt specifier (see interrupt bindings for
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details)
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- interrupt-controller : Marks the device node as an interrupt controller.
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- #interrupt-cells : Should be 2. The first cell is the GPIO number.
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The second cell bits[3:0] is used to specify trigger type and level flags:
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1 = low-to-high edge triggered.
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2 = high-to-low edge triggered.
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4 = active high level-sensitive.
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8 = active low level-sensitive.
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- reg : Address and length of the register set for the device
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Example:
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gpio@e000a000 {
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#gpio-cells = <2>;
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compatible = "xlnx,zynq-gpio-1.0";
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clocks = <&clkc 42>;
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gpio-controller;
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interrupt-parent = <&intc>;
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interrupts = <0 20 4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xe000a000 0x1000>;
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};
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