ed9d205363
- Update SRIOV PF2VF header with latest revision - Extend existing function in amdgpu_virt.c to read MM bandwidth config from PF2VF message - Add SRIOV Sienna Cichlid codec array and update the bandwidth with PF2VF message v2: squash in removal of unused variable (Alex) Signed-off-by: Bokun Zhang <bokun.zhang@amd.com> Reviewed-by: Monk liu <monk.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
332 lines
9.5 KiB
C
332 lines
9.5 KiB
C
/*
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* Copyright 2018-2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef AMDGV_SRIOV_MSG__H_
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#define AMDGV_SRIOV_MSG__H_
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/* unit in kilobytes */
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#define AMD_SRIOV_MSG_VBIOS_OFFSET 0
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#define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64
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#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB
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#define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4
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/*
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* layout
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* 0 64KB 65KB 66KB
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* | VBIOS | PF2VF | VF2PF | Bad Page | ...
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* | 64KB | 1KB | 1KB |
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*/
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#define AMD_SRIOV_MSG_SIZE_KB 1
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#define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB
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#define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
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#define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
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/*
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* PF2VF history log:
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* v1 defined in amdgim
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* v2 current
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*
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* VF2PF history log:
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* v1 defined in amdgim
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* v2 defined in amdgim
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* v3 current
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*/
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#define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2
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#define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3
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#define AMD_SRIOV_MSG_RESERVE_UCODE 24
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#define AMD_SRIOV_MSG_RESERVE_VCN_INST 4
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enum amd_sriov_ucode_engine_id {
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AMD_SRIOV_UCODE_ID_VCE = 0,
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AMD_SRIOV_UCODE_ID_UVD,
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AMD_SRIOV_UCODE_ID_MC,
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AMD_SRIOV_UCODE_ID_ME,
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AMD_SRIOV_UCODE_ID_PFP,
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AMD_SRIOV_UCODE_ID_CE,
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AMD_SRIOV_UCODE_ID_RLC,
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AMD_SRIOV_UCODE_ID_RLC_SRLC,
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AMD_SRIOV_UCODE_ID_RLC_SRLG,
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AMD_SRIOV_UCODE_ID_RLC_SRLS,
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AMD_SRIOV_UCODE_ID_MEC,
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AMD_SRIOV_UCODE_ID_MEC2,
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AMD_SRIOV_UCODE_ID_SOS,
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AMD_SRIOV_UCODE_ID_ASD,
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AMD_SRIOV_UCODE_ID_TA_RAS,
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AMD_SRIOV_UCODE_ID_TA_XGMI,
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AMD_SRIOV_UCODE_ID_SMC,
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AMD_SRIOV_UCODE_ID_SDMA,
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AMD_SRIOV_UCODE_ID_SDMA2,
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AMD_SRIOV_UCODE_ID_VCN,
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AMD_SRIOV_UCODE_ID_DMCU,
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AMD_SRIOV_UCODE_ID__MAX
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};
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#pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed
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union amd_sriov_msg_feature_flags {
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struct {
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uint32_t error_log_collect : 1;
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uint32_t host_load_ucodes : 1;
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uint32_t host_flr_vramlost : 1;
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uint32_t mm_bw_management : 1;
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uint32_t pp_one_vf_mode : 1;
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uint32_t reg_indirect_acc : 1;
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uint32_t reserved : 26;
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} flags;
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uint32_t all;
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};
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union amd_sriov_reg_access_flags {
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struct {
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uint32_t vf_reg_access_ih : 1;
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uint32_t vf_reg_access_mmhub : 1;
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uint32_t vf_reg_access_gc : 1;
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uint32_t reserved : 29;
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} flags;
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uint32_t all;
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};
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union amd_sriov_msg_os_info {
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struct {
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uint32_t windows : 1;
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uint32_t reserved : 31;
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} info;
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uint32_t all;
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};
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struct amd_sriov_msg_uuid_info {
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union {
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struct {
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uint32_t did : 16;
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uint32_t fcn : 8;
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uint32_t asic_7 : 8;
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};
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uint32_t time_low;
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};
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struct {
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uint32_t time_mid : 16;
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uint32_t time_high : 12;
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uint32_t version : 4;
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};
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struct {
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struct {
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uint8_t clk_seq_hi : 6;
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uint8_t variant : 2;
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};
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union {
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uint8_t clk_seq_low;
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uint8_t asic_6;
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};
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uint16_t asic_4;
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};
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uint32_t asic_0;
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};
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struct amd_sriov_msg_pf2vf_info_header {
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/* the total structure size in byte */
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uint32_t size;
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/* version of this structure, written by the HOST */
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uint32_t version;
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/* reserved */
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uint32_t reserved[2];
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};
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struct amd_sriov_msg_pf2vf_info {
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/* header contains size and version */
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struct amd_sriov_msg_pf2vf_info_header header;
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/* use private key from mailbox 2 to create checksum */
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uint32_t checksum;
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/* The features flags of the HOST driver supports */
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union amd_sriov_msg_feature_flags feature_flags;
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/* (max_width * max_height * fps) / (16 * 16) */
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uint32_t hevc_enc_max_mb_per_second;
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/* (max_width * max_height) / (16 * 16) */
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uint32_t hevc_enc_max_mb_per_frame;
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/* (max_width * max_height * fps) / (16 * 16) */
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uint32_t avc_enc_max_mb_per_second;
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/* (max_width * max_height) / (16 * 16) */
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uint32_t avc_enc_max_mb_per_frame;
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/* MEC FW position in BYTE from the start of VF visible frame buffer */
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uint64_t mecfw_offset;
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/* MEC FW size in BYTE */
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uint32_t mecfw_size;
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/* UVD FW position in BYTE from the start of VF visible frame buffer */
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uint64_t uvdfw_offset;
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/* UVD FW size in BYTE */
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uint32_t uvdfw_size;
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/* VCE FW position in BYTE from the start of VF visible frame buffer */
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uint64_t vcefw_offset;
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/* VCE FW size in BYTE */
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uint32_t vcefw_size;
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/* Bad pages block position in BYTE */
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uint32_t bp_block_offset_low;
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uint32_t bp_block_offset_high;
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/* Bad pages block size in BYTE */
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uint32_t bp_block_size;
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/* frequency for VF to update the VF2PF area in msec, 0 = manual */
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uint32_t vf2pf_update_interval_ms;
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/* identification in ROCm SMI */
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uint64_t uuid;
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uint32_t fcn_idx;
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/* flags to indicate which register access method VF should use */
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union amd_sriov_reg_access_flags reg_access_flags;
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/* MM BW management */
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struct {
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uint32_t decode_max_dimension_pixels;
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uint32_t decode_max_frame_pixels;
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uint32_t encode_max_dimension_pixels;
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uint32_t encode_max_frame_pixels;
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} mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST];
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/* UUID info */
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struct amd_sriov_msg_uuid_info uuid_info;
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/* reserved */
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uint32_t reserved[256 - 47];
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};
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struct amd_sriov_msg_vf2pf_info_header {
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/* the total structure size in byte */
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uint32_t size;
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/* version of this structure, written by the guest */
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uint32_t version;
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/* reserved */
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uint32_t reserved[2];
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};
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struct amd_sriov_msg_vf2pf_info {
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/* header contains size and version */
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struct amd_sriov_msg_vf2pf_info_header header;
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uint32_t checksum;
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/* driver version */
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uint8_t driver_version[64];
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/* driver certification, 1=WHQL, 0=None */
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uint32_t driver_cert;
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/* guest OS type and version */
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union amd_sriov_msg_os_info os_info;
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/* guest fb information in the unit of MB */
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uint32_t fb_usage;
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/* guest gfx engine usage percentage */
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uint32_t gfx_usage;
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/* guest gfx engine health percentage */
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uint32_t gfx_health;
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/* guest compute engine usage percentage */
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uint32_t compute_usage;
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/* guest compute engine health percentage */
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uint32_t compute_health;
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/* guest avc engine usage percentage. 0xffff means N/A */
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uint32_t avc_enc_usage;
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/* guest avc engine health percentage. 0xffff means N/A */
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uint32_t avc_enc_health;
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/* guest hevc engine usage percentage. 0xffff means N/A */
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uint32_t hevc_enc_usage;
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/* guest hevc engine usage percentage. 0xffff means N/A */
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uint32_t hevc_enc_health;
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/* combined encode/decode usage */
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uint32_t encode_usage;
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uint32_t decode_usage;
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/* Version of PF2VF that VF understands */
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uint32_t pf2vf_version_required;
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/* additional FB usage */
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uint32_t fb_vis_usage;
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uint32_t fb_vis_size;
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uint32_t fb_size;
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/* guest ucode data, each one is 1.25 Dword */
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struct {
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uint8_t id;
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uint32_t version;
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} ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
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/* reserved */
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uint32_t reserved[256-68];
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};
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/* mailbox message send from guest to host */
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enum amd_sriov_mailbox_request_message {
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MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1,
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MB_REQ_MSG_REL_GPU_INIT_ACCESS,
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MB_REQ_MSG_REQ_GPU_FINI_ACCESS,
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MB_REQ_MSG_REL_GPU_FINI_ACCESS,
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MB_REQ_MSG_REQ_GPU_RESET_ACCESS,
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MB_REQ_MSG_REQ_GPU_INIT_DATA,
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MB_REQ_MSG_LOG_VF_ERROR = 200,
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};
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/* mailbox message send from host to guest */
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enum amd_sriov_mailbox_response_message {
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MB_RES_MSG_CLR_MSG_BUF = 0,
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MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
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MB_RES_MSG_FLR_NOTIFICATION,
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MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,
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MB_RES_MSG_SUCCESS,
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MB_RES_MSG_FAIL,
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MB_RES_MSG_QUERY_ALIVE,
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MB_RES_MSG_GPU_INIT_DATA_READY,
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MB_RES_MSG_TEXT_MESSAGE = 255
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};
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/* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */
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enum amd_sriov_gpu_init_data_version {
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GPU_INIT_DATA_READY_V1 = 1,
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};
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#pragma pack(pop) // Restore previous packing option
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/* checksum function between host and guest */
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unsigned int amd_sriov_msg_checksum(void *obj,
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unsigned long obj_size,
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unsigned int key,
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unsigned int checksum);
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/* assertion at compile time */
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#ifdef __linux__
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#define stringification(s) _stringification(s)
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#define _stringification(s) #s
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_Static_assert(
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sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
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"amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
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_Static_assert(
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sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
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"amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
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_Static_assert(
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AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0,
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"AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4");
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_Static_assert(
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AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX,
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"AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX");
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#undef _stringification
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#undef stringification
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#endif
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#endif /* AMDGV_SRIOV_MSG__H_ */
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