Shawn Lin 64d6ea602c PCI: rockchip: Set PCI_EXP_LNKSTA_SLC in the Root Port
All platforms using Rockchip use a common clock for the Root Port and the
slot connected to it. Indicate this by setting the Slot Clock Configuration
(PCI_EXP_LNKSTA_SLC) bit in the Root Port's Link Status.

Per the Implementation Note in the spec (PCIe r3.1, sec 7.8.7), if the
downstream component also sets PCI_EXP_LNKSTA_SLC, software may set the
Common Clock Configuration (PCI_EXP_LNKCTL_CCC) bits on both ends of the
Link. This is done by pcie_aspm_configure_common_clock().

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Brian Norris <briannorris@chromium.org>
Cc: jeffy.chen <jeffy.chen@rock-chips.com>
2017-04-11 16:27:02 -05:00
..
2017-03-03 21:36:56 -08:00
2017-03-03 21:36:56 -08:00
2017-02-23 15:57:04 -08:00
2017-03-03 16:15:48 -08:00
2017-03-04 11:26:18 -08:00
2017-02-20 16:42:43 -08:00
2017-02-23 15:57:04 -08:00
2017-02-21 11:51:42 -08:00
2017-02-22 19:23:14 -08:00
2017-02-23 11:53:22 -08:00
2017-03-01 09:46:02 -08:00
2017-02-20 17:23:57 -08:00
2017-02-23 15:57:04 -08:00
2017-03-02 13:53:13 -08:00
2017-03-03 21:36:56 -08:00
2017-02-23 11:53:22 -08:00