65ac79e181
This patch add the support for phylink_get_caps for ksz8795 and ksz9477 series switch. It updates the struct ksz_switch_chip with the details of the internal phys and xmii interface. Then during the get_caps based on the bits set in the structure, corresponding phy mode is set. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1486 lines
38 KiB
C
1486 lines
38 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Microchip KSZ9477 switch driver main logic
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*
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* Copyright (C) 2017-2019 Microchip Technology Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/iopoll.h>
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#include <linux/platform_data/microchip-ksz.h>
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#include <linux/phy.h>
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#include <linux/if_bridge.h>
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#include <linux/if_vlan.h>
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#include <net/dsa.h>
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#include <net/switchdev.h>
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#include "ksz9477_reg.h"
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#include "ksz_common.h"
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/* Used with variable features to indicate capabilities. */
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#define GBIT_SUPPORT BIT(0)
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#define NEW_XMII BIT(1)
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#define IS_9893 BIT(2)
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static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
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{
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regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
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}
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static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
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bool set)
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{
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regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
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bits, set ? bits : 0);
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}
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static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
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{
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regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0);
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}
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static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset,
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u32 bits, bool set)
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{
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regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset),
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bits, set ? bits : 0);
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}
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static int ksz9477_change_mtu(struct dsa_switch *ds, int port, int mtu)
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{
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struct ksz_device *dev = ds->priv;
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u16 frame_size, max_frame = 0;
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int i;
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frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
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/* Cache the per-port MTU setting */
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dev->ports[port].max_frame = frame_size;
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for (i = 0; i < dev->info->port_cnt; i++)
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max_frame = max(max_frame, dev->ports[i].max_frame);
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return regmap_update_bits(dev->regmap[1], REG_SW_MTU__2,
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REG_SW_MTU_MASK, max_frame);
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}
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static int ksz9477_max_mtu(struct dsa_switch *ds, int port)
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{
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return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
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}
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static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev)
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{
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unsigned int val;
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return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL,
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val, !(val & VLAN_START), 10, 1000);
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}
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static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid,
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u32 *vlan_table)
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{
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int ret;
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mutex_lock(&dev->vlan_mutex);
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ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
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ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
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/* wait to be cleared */
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ret = ksz9477_wait_vlan_ctrl_ready(dev);
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if (ret) {
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dev_dbg(dev->dev, "Failed to read vlan table\n");
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goto exit;
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}
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ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
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ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
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ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
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ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
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exit:
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mutex_unlock(&dev->vlan_mutex);
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return ret;
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}
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static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid,
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u32 *vlan_table)
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{
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int ret;
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mutex_lock(&dev->vlan_mutex);
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ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
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ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
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ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
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ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
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ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
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/* wait to be cleared */
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ret = ksz9477_wait_vlan_ctrl_ready(dev);
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if (ret) {
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dev_dbg(dev->dev, "Failed to write vlan table\n");
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goto exit;
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}
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ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
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/* update vlan cache table */
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dev->vlan_cache[vid].table[0] = vlan_table[0];
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dev->vlan_cache[vid].table[1] = vlan_table[1];
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dev->vlan_cache[vid].table[2] = vlan_table[2];
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exit:
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mutex_unlock(&dev->vlan_mutex);
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return ret;
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}
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static void ksz9477_read_table(struct ksz_device *dev, u32 *table)
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{
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ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
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ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
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ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
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ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
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}
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static void ksz9477_write_table(struct ksz_device *dev, u32 *table)
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{
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ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
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ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
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ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
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ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
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}
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static int ksz9477_wait_alu_ready(struct ksz_device *dev)
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{
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unsigned int val;
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return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4,
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val, !(val & ALU_START), 10, 1000);
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}
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static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev)
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{
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unsigned int val;
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return regmap_read_poll_timeout(dev->regmap[2],
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REG_SW_ALU_STAT_CTRL__4,
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val, !(val & ALU_STAT_START),
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10, 1000);
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}
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static int ksz9477_reset_switch(struct ksz_device *dev)
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{
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u8 data8;
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u32 data32;
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/* reset switch */
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ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
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/* turn off SPI DO Edge select */
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regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0,
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SPI_AUTO_EDGE_DETECTION, 0);
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/* default configuration */
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ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
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data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
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SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
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ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
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/* disable interrupts */
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ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
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ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
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ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
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/* set broadcast storm protection 10% rate */
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regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2,
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BROADCAST_STORM_RATE,
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(BROADCAST_STORM_VALUE *
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BROADCAST_STORM_PROT_RATE) / 100);
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data8 = SW_ENABLE_REFCLKO;
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if (dev->synclko_disable)
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data8 = 0;
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else if (dev->synclko_125)
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data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ;
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ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8);
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return 0;
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}
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static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
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u64 *cnt)
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{
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struct ksz_port *p = &dev->ports[port];
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unsigned int val;
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u32 data;
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int ret;
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/* retain the flush/freeze bit */
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data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
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data |= MIB_COUNTER_READ;
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data |= (addr << MIB_COUNTER_INDEX_S);
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ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
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ret = regmap_read_poll_timeout(dev->regmap[2],
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PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4),
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val, !(val & MIB_COUNTER_READ), 10, 1000);
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/* failed to read MIB. get out of loop */
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if (ret) {
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dev_dbg(dev->dev, "Failed to get MIB\n");
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return;
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}
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/* count resets upon read */
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ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
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*cnt += data;
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}
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static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
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u64 *dropped, u64 *cnt)
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{
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addr = dev->info->mib_names[addr].index;
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ksz9477_r_mib_cnt(dev, port, addr, cnt);
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}
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static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze)
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{
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u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
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struct ksz_port *p = &dev->ports[port];
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/* enable/disable the port for flush/freeze function */
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mutex_lock(&p->mib.cnt_mutex);
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ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val);
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/* used by MIB counter reading code to know freeze is enabled */
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p->freeze = freeze;
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mutex_unlock(&p->mib.cnt_mutex);
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}
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static void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
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{
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struct ksz_port_mib *mib = &dev->ports[port].mib;
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/* flush all enabled port MIB counters */
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mutex_lock(&mib->cnt_mutex);
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ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
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MIB_COUNTER_FLUSH_FREEZE);
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ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
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ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
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mutex_unlock(&mib->cnt_mutex);
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}
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static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds,
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int port,
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enum dsa_tag_protocol mp)
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{
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enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477;
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struct ksz_device *dev = ds->priv;
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if (dev->features & IS_9893)
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proto = DSA_TAG_PROTO_KSZ9893;
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return proto;
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}
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static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg)
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{
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struct ksz_device *dev = ds->priv;
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u16 val = 0xffff;
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/* No real PHY after this. Simulate the PHY.
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* A fixed PHY can be setup in the device tree, but this function is
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* still called for that port during initialization.
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* For RGMII PHY there is no way to access it so the fixed PHY should
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* be used. For SGMII PHY the supporting code will be added later.
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*/
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if (addr >= dev->phy_port_cnt) {
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struct ksz_port *p = &dev->ports[addr];
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switch (reg) {
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case MII_BMCR:
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val = 0x1140;
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break;
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case MII_BMSR:
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val = 0x796d;
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break;
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case MII_PHYSID1:
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val = 0x0022;
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break;
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case MII_PHYSID2:
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val = 0x1631;
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break;
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case MII_ADVERTISE:
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val = 0x05e1;
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break;
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case MII_LPA:
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val = 0xc5e1;
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break;
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case MII_CTRL1000:
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val = 0x0700;
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break;
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case MII_STAT1000:
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if (p->phydev.speed == SPEED_1000)
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val = 0x3800;
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else
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val = 0;
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break;
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}
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} else {
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ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
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}
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return val;
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}
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static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg,
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u16 val)
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{
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struct ksz_device *dev = ds->priv;
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/* No real PHY after this. */
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if (addr >= dev->phy_port_cnt)
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return 0;
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/* No gigabit support. Do not write to this register. */
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if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
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return 0;
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ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
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return 0;
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}
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static void ksz9477_cfg_port_member(struct ksz_device *dev, int port,
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u8 member)
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{
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ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
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}
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static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port,
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u8 state)
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{
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ksz_port_stp_state_set(ds, port, state, P_STP_CTRL);
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}
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static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
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{
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u8 data;
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regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2,
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SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S,
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SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S);
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if (port < dev->info->port_cnt) {
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/* flush individual port */
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ksz_pread8(dev, port, P_STP_CTRL, &data);
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if (!(data & PORT_LEARN_DISABLE))
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ksz_pwrite8(dev, port, P_STP_CTRL,
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data | PORT_LEARN_DISABLE);
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ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
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ksz_pwrite8(dev, port, P_STP_CTRL, data);
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} else {
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/* flush all */
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ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
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}
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}
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static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port,
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bool flag,
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struct netlink_ext_ack *extack)
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{
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struct ksz_device *dev = ds->priv;
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if (flag) {
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ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
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PORT_VLAN_LOOKUP_VID_0, true);
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ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
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} else {
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ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
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ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
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PORT_VLAN_LOOKUP_VID_0, false);
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}
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return 0;
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}
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static int ksz9477_port_vlan_add(struct dsa_switch *ds, int port,
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const struct switchdev_obj_port_vlan *vlan,
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struct netlink_ext_ack *extack)
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{
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struct ksz_device *dev = ds->priv;
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u32 vlan_table[3];
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bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
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int err;
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err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table);
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if (err) {
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NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table");
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return err;
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}
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vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M);
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if (untagged)
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vlan_table[1] |= BIT(port);
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else
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vlan_table[1] &= ~BIT(port);
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vlan_table[1] &= ~(BIT(dev->cpu_port));
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vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
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err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table);
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if (err) {
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NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table");
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return err;
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}
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/* change PVID */
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if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
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ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid);
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return 0;
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}
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static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port,
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const struct switchdev_obj_port_vlan *vlan)
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{
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struct ksz_device *dev = ds->priv;
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bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
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u32 vlan_table[3];
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u16 pvid;
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ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
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pvid = pvid & 0xFFF;
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|
|
if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) {
|
|
dev_dbg(dev->dev, "Failed to get vlan table\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
vlan_table[2] &= ~BIT(port);
|
|
|
|
if (pvid == vlan->vid)
|
|
pvid = 1;
|
|
|
|
if (untagged)
|
|
vlan_table[1] &= ~BIT(port);
|
|
|
|
if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) {
|
|
dev_dbg(dev->dev, "Failed to set vlan table\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port,
|
|
const unsigned char *addr, u16 vid,
|
|
struct dsa_db db)
|
|
{
|
|
struct ksz_device *dev = ds->priv;
|
|
u32 alu_table[4];
|
|
u32 data;
|
|
int ret = 0;
|
|
|
|
mutex_lock(&dev->alu_mutex);
|
|
|
|
/* find any entry with mac & vid */
|
|
data = vid << ALU_FID_INDEX_S;
|
|
data |= ((addr[0] << 8) | addr[1]);
|
|
ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
|
|
|
|
data = ((addr[2] << 24) | (addr[3] << 16));
|
|
data |= ((addr[4] << 8) | addr[5]);
|
|
ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
|
|
|
|
/* start read operation */
|
|
ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
|
|
|
|
/* wait to be finished */
|
|
ret = ksz9477_wait_alu_ready(dev);
|
|
if (ret) {
|
|
dev_dbg(dev->dev, "Failed to read ALU\n");
|
|
goto exit;
|
|
}
|
|
|
|
/* read ALU entry */
|
|
ksz9477_read_table(dev, alu_table);
|
|
|
|
/* update ALU entry */
|
|
alu_table[0] = ALU_V_STATIC_VALID;
|
|
alu_table[1] |= BIT(port);
|
|
if (vid)
|
|
alu_table[1] |= ALU_V_USE_FID;
|
|
alu_table[2] = (vid << ALU_V_FID_S);
|
|
alu_table[2] |= ((addr[0] << 8) | addr[1]);
|
|
alu_table[3] = ((addr[2] << 24) | (addr[3] << 16));
|
|
alu_table[3] |= ((addr[4] << 8) | addr[5]);
|
|
|
|
ksz9477_write_table(dev, alu_table);
|
|
|
|
ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
|
|
|
|
/* wait to be finished */
|
|
ret = ksz9477_wait_alu_ready(dev);
|
|
if (ret)
|
|
dev_dbg(dev->dev, "Failed to write ALU\n");
|
|
|
|
exit:
|
|
mutex_unlock(&dev->alu_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port,
|
|
const unsigned char *addr, u16 vid,
|
|
struct dsa_db db)
|
|
{
|
|
struct ksz_device *dev = ds->priv;
|
|
u32 alu_table[4];
|
|
u32 data;
|
|
int ret = 0;
|
|
|
|
mutex_lock(&dev->alu_mutex);
|
|
|
|
/* read any entry with mac & vid */
|
|
data = vid << ALU_FID_INDEX_S;
|
|
data |= ((addr[0] << 8) | addr[1]);
|
|
ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
|
|
|
|
data = ((addr[2] << 24) | (addr[3] << 16));
|
|
data |= ((addr[4] << 8) | addr[5]);
|
|
ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
|
|
|
|
/* start read operation */
|
|
ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
|
|
|
|
/* wait to be finished */
|
|
ret = ksz9477_wait_alu_ready(dev);
|
|
if (ret) {
|
|
dev_dbg(dev->dev, "Failed to read ALU\n");
|
|
goto exit;
|
|
}
|
|
|
|
ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
|
|
if (alu_table[0] & ALU_V_STATIC_VALID) {
|
|
ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
|
|
ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
|
|
ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
|
|
|
|
/* clear forwarding port */
|
|
alu_table[2] &= ~BIT(port);
|
|
|
|
/* if there is no port to forward, clear table */
|
|
if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
|
|
alu_table[0] = 0;
|
|
alu_table[1] = 0;
|
|
alu_table[2] = 0;
|
|
alu_table[3] = 0;
|
|
}
|
|
} else {
|
|
alu_table[0] = 0;
|
|
alu_table[1] = 0;
|
|
alu_table[2] = 0;
|
|
alu_table[3] = 0;
|
|
}
|
|
|
|
ksz9477_write_table(dev, alu_table);
|
|
|
|
ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
|
|
|
|
/* wait to be finished */
|
|
ret = ksz9477_wait_alu_ready(dev);
|
|
if (ret)
|
|
dev_dbg(dev->dev, "Failed to write ALU\n");
|
|
|
|
exit:
|
|
mutex_unlock(&dev->alu_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table)
|
|
{
|
|
alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
|
|
alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
|
|
alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
|
|
alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
|
|
ALU_V_PRIO_AGE_CNT_M;
|
|
alu->mstp = alu_table[0] & ALU_V_MSTP_M;
|
|
|
|
alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
|
|
alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
|
|
alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
|
|
|
|
alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
|
|
|
|
alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
|
|
alu->mac[1] = alu_table[2] & 0xFF;
|
|
alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
|
|
alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
|
|
alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
|
|
alu->mac[5] = alu_table[3] & 0xFF;
|
|
}
|
|
|
|
static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port,
|
|
dsa_fdb_dump_cb_t *cb, void *data)
|
|
{
|
|
struct ksz_device *dev = ds->priv;
|
|
int ret = 0;
|
|
u32 ksz_data;
|
|
u32 alu_table[4];
|
|
struct alu_struct alu;
|
|
int timeout;
|
|
|
|
mutex_lock(&dev->alu_mutex);
|
|
|
|
/* start ALU search */
|
|
ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
|
|
|
|
do {
|
|
timeout = 1000;
|
|
do {
|
|
ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
|
|
if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START))
|
|
break;
|
|
usleep_range(1, 10);
|
|
} while (timeout-- > 0);
|
|
|
|
if (!timeout) {
|
|
dev_dbg(dev->dev, "Failed to search ALU\n");
|
|
ret = -ETIMEDOUT;
|
|
goto exit;
|
|
}
|
|
|
|
/* read ALU table */
|
|
ksz9477_read_table(dev, alu_table);
|
|
|
|
ksz9477_convert_alu(&alu, alu_table);
|
|
|
|
if (alu.port_forward & BIT(port)) {
|
|
ret = cb(alu.mac, alu.fid, alu.is_static, data);
|
|
if (ret)
|
|
goto exit;
|
|
}
|
|
} while (ksz_data & ALU_START);
|
|
|
|
exit:
|
|
|
|
/* stop ALU search */
|
|
ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
|
|
|
|
mutex_unlock(&dev->alu_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ksz9477_port_mdb_add(struct dsa_switch *ds, int port,
|
|
const struct switchdev_obj_port_mdb *mdb,
|
|
struct dsa_db db)
|
|
{
|
|
struct ksz_device *dev = ds->priv;
|
|
u32 static_table[4];
|
|
u32 data;
|
|
int index;
|
|
u32 mac_hi, mac_lo;
|
|
int err = 0;
|
|
|
|
mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
|
|
mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
|
|
mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
|
|
|
|
mutex_lock(&dev->alu_mutex);
|
|
|
|
for (index = 0; index < dev->info->num_statics; index++) {
|
|
/* find empty slot first */
|
|
data = (index << ALU_STAT_INDEX_S) |
|
|
ALU_STAT_READ | ALU_STAT_START;
|
|
ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
|
|
|
|
/* wait to be finished */
|
|
err = ksz9477_wait_alu_sta_ready(dev);
|
|
if (err) {
|
|
dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
|
|
goto exit;
|
|
}
|
|
|
|
/* read ALU static table */
|
|
ksz9477_read_table(dev, static_table);
|
|
|
|
if (static_table[0] & ALU_V_STATIC_VALID) {
|
|
/* check this has same vid & mac address */
|
|
if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
|
|
((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
|
|
static_table[3] == mac_lo) {
|
|
/* found matching one */
|
|
break;
|
|
}
|
|
} else {
|
|
/* found empty one */
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* no available entry */
|
|
if (index == dev->info->num_statics) {
|
|
err = -ENOSPC;
|
|
goto exit;
|
|
}
|
|
|
|
/* add entry */
|
|
static_table[0] = ALU_V_STATIC_VALID;
|
|
static_table[1] |= BIT(port);
|
|
if (mdb->vid)
|
|
static_table[1] |= ALU_V_USE_FID;
|
|
static_table[2] = (mdb->vid << ALU_V_FID_S);
|
|
static_table[2] |= mac_hi;
|
|
static_table[3] = mac_lo;
|
|
|
|
ksz9477_write_table(dev, static_table);
|
|
|
|
data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
|
|
ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
|
|
|
|
/* wait to be finished */
|
|
if (ksz9477_wait_alu_sta_ready(dev))
|
|
dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
|
|
|
|
exit:
|
|
mutex_unlock(&dev->alu_mutex);
|
|
return err;
|
|
}
|
|
|
|
static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port,
|
|
const struct switchdev_obj_port_mdb *mdb,
|
|
struct dsa_db db)
|
|
{
|
|
struct ksz_device *dev = ds->priv;
|
|
u32 static_table[4];
|
|
u32 data;
|
|
int index;
|
|
int ret = 0;
|
|
u32 mac_hi, mac_lo;
|
|
|
|
mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
|
|
mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
|
|
mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
|
|
|
|
mutex_lock(&dev->alu_mutex);
|
|
|
|
for (index = 0; index < dev->info->num_statics; index++) {
|
|
/* find empty slot first */
|
|
data = (index << ALU_STAT_INDEX_S) |
|
|
ALU_STAT_READ | ALU_STAT_START;
|
|
ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
|
|
|
|
/* wait to be finished */
|
|
ret = ksz9477_wait_alu_sta_ready(dev);
|
|
if (ret) {
|
|
dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
|
|
goto exit;
|
|
}
|
|
|
|
/* read ALU static table */
|
|
ksz9477_read_table(dev, static_table);
|
|
|
|
if (static_table[0] & ALU_V_STATIC_VALID) {
|
|
/* check this has same vid & mac address */
|
|
|
|
if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
|
|
((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
|
|
static_table[3] == mac_lo) {
|
|
/* found matching one */
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* no available entry */
|
|
if (index == dev->info->num_statics)
|
|
goto exit;
|
|
|
|
/* clear port */
|
|
static_table[1] &= ~BIT(port);
|
|
|
|
if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
|
|
/* delete entry */
|
|
static_table[0] = 0;
|
|
static_table[1] = 0;
|
|
static_table[2] = 0;
|
|
static_table[3] = 0;
|
|
}
|
|
|
|
ksz9477_write_table(dev, static_table);
|
|
|
|
data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
|
|
ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
|
|
|
|
/* wait to be finished */
|
|
ret = ksz9477_wait_alu_sta_ready(dev);
|
|
if (ret)
|
|
dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
|
|
|
|
exit:
|
|
mutex_unlock(&dev->alu_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port,
|
|
struct dsa_mall_mirror_tc_entry *mirror,
|
|
bool ingress, struct netlink_ext_ack *extack)
|
|
{
|
|
struct ksz_device *dev = ds->priv;
|
|
u8 data;
|
|
int p;
|
|
|
|
/* Limit to one sniffer port
|
|
* Check if any of the port is already set for sniffing
|
|
* If yes, instruct the user to remove the previous entry & exit
|
|
*/
|
|
for (p = 0; p < dev->info->port_cnt; p++) {
|
|
/* Skip the current sniffing port */
|
|
if (p == mirror->to_local_port)
|
|
continue;
|
|
|
|
ksz_pread8(dev, p, P_MIRROR_CTRL, &data);
|
|
|
|
if (data & PORT_MIRROR_SNIFFER) {
|
|
NL_SET_ERR_MSG_MOD(extack,
|
|
"Sniffer port is already configured, delete existing rules & retry");
|
|
return -EBUSY;
|
|
}
|
|
}
|
|
|
|
if (ingress)
|
|
ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
|
|
else
|
|
ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
|
|
|
|
/* configure mirror port */
|
|
ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
|
|
PORT_MIRROR_SNIFFER, true);
|
|
|
|
ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port,
|
|
struct dsa_mall_mirror_tc_entry *mirror)
|
|
{
|
|
struct ksz_device *dev = ds->priv;
|
|
bool in_use = false;
|
|
u8 data;
|
|
int p;
|
|
|
|
if (mirror->ingress)
|
|
ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
|
|
else
|
|
ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
|
|
|
|
|
|
/* Check if any of the port is still referring to sniffer port */
|
|
for (p = 0; p < dev->info->port_cnt; p++) {
|
|
ksz_pread8(dev, p, P_MIRROR_CTRL, &data);
|
|
|
|
if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) {
|
|
in_use = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* delete sniffing if there are no other mirroring rules */
|
|
if (!in_use)
|
|
ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
|
|
PORT_MIRROR_SNIFFER, false);
|
|
}
|
|
|
|
static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
|
|
{
|
|
bool gbit;
|
|
|
|
if (dev->features & NEW_XMII)
|
|
gbit = !(data & PORT_MII_NOT_1GBIT);
|
|
else
|
|
gbit = !!(data & PORT_MII_1000MBIT_S1);
|
|
return gbit;
|
|
}
|
|
|
|
static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
|
|
{
|
|
if (dev->features & NEW_XMII) {
|
|
if (gbit)
|
|
*data &= ~PORT_MII_NOT_1GBIT;
|
|
else
|
|
*data |= PORT_MII_NOT_1GBIT;
|
|
} else {
|
|
if (gbit)
|
|
*data |= PORT_MII_1000MBIT_S1;
|
|
else
|
|
*data &= ~PORT_MII_1000MBIT_S1;
|
|
}
|
|
}
|
|
|
|
static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
|
|
{
|
|
int mode;
|
|
|
|
if (dev->features & NEW_XMII) {
|
|
switch (data & PORT_MII_SEL_M) {
|
|
case PORT_MII_SEL:
|
|
mode = 0;
|
|
break;
|
|
case PORT_RMII_SEL:
|
|
mode = 1;
|
|
break;
|
|
case PORT_GMII_SEL:
|
|
mode = 2;
|
|
break;
|
|
default:
|
|
mode = 3;
|
|
}
|
|
} else {
|
|
switch (data & PORT_MII_SEL_M) {
|
|
case PORT_MII_SEL_S1:
|
|
mode = 0;
|
|
break;
|
|
case PORT_RMII_SEL_S1:
|
|
mode = 1;
|
|
break;
|
|
case PORT_GMII_SEL_S1:
|
|
mode = 2;
|
|
break;
|
|
default:
|
|
mode = 3;
|
|
}
|
|
}
|
|
return mode;
|
|
}
|
|
|
|
static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
|
|
{
|
|
u8 xmii;
|
|
|
|
if (dev->features & NEW_XMII) {
|
|
switch (mode) {
|
|
case 0:
|
|
xmii = PORT_MII_SEL;
|
|
break;
|
|
case 1:
|
|
xmii = PORT_RMII_SEL;
|
|
break;
|
|
case 2:
|
|
xmii = PORT_GMII_SEL;
|
|
break;
|
|
default:
|
|
xmii = PORT_RGMII_SEL;
|
|
break;
|
|
}
|
|
} else {
|
|
switch (mode) {
|
|
case 0:
|
|
xmii = PORT_MII_SEL_S1;
|
|
break;
|
|
case 1:
|
|
xmii = PORT_RMII_SEL_S1;
|
|
break;
|
|
case 2:
|
|
xmii = PORT_GMII_SEL_S1;
|
|
break;
|
|
default:
|
|
xmii = PORT_RGMII_SEL_S1;
|
|
break;
|
|
}
|
|
}
|
|
*data &= ~PORT_MII_SEL_M;
|
|
*data |= xmii;
|
|
}
|
|
|
|
static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
|
|
{
|
|
phy_interface_t interface;
|
|
bool gbit;
|
|
int mode;
|
|
u8 data8;
|
|
|
|
if (port < dev->phy_port_cnt)
|
|
return PHY_INTERFACE_MODE_NA;
|
|
ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
|
|
gbit = ksz9477_get_gbit(dev, data8);
|
|
mode = ksz9477_get_xmii(dev, data8);
|
|
switch (mode) {
|
|
case 2:
|
|
interface = PHY_INTERFACE_MODE_GMII;
|
|
if (gbit)
|
|
break;
|
|
fallthrough;
|
|
case 0:
|
|
interface = PHY_INTERFACE_MODE_MII;
|
|
break;
|
|
case 1:
|
|
interface = PHY_INTERFACE_MODE_RMII;
|
|
break;
|
|
default:
|
|
interface = PHY_INTERFACE_MODE_RGMII;
|
|
if (data8 & PORT_RGMII_ID_EG_ENABLE)
|
|
interface = PHY_INTERFACE_MODE_RGMII_TXID;
|
|
if (data8 & PORT_RGMII_ID_IG_ENABLE) {
|
|
interface = PHY_INTERFACE_MODE_RGMII_RXID;
|
|
if (data8 & PORT_RGMII_ID_EG_ENABLE)
|
|
interface = PHY_INTERFACE_MODE_RGMII_ID;
|
|
}
|
|
break;
|
|
}
|
|
return interface;
|
|
}
|
|
|
|
static void ksz9477_port_mmd_write(struct ksz_device *dev, int port,
|
|
u8 dev_addr, u16 reg_addr, u16 val)
|
|
{
|
|
ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
|
|
MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr));
|
|
ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr);
|
|
ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
|
|
MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr));
|
|
ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
|
|
}
|
|
|
|
static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port)
|
|
{
|
|
/* Apply PHY settings to address errata listed in
|
|
* KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
|
|
* Silicon Errata and Data Sheet Clarification documents:
|
|
*
|
|
* Register settings are needed to improve PHY receive performance
|
|
*/
|
|
ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
|
|
ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
|
|
ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
|
|
ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
|
|
ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
|
|
|
|
/* Transmit waveform amplitude can be improved
|
|
* (1000BASE-T, 100BASE-TX, 10BASE-Te)
|
|
*/
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
|
|
|
|
/* Energy Efficient Ethernet (EEE) feature select must
|
|
* be manually disabled (except on KSZ8565 which is 100Mbit)
|
|
*/
|
|
if (dev->features & GBIT_SUPPORT)
|
|
ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
|
|
|
|
/* Register settings are required to meet data sheet
|
|
* supply current specifications
|
|
*/
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
|
|
ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
|
|
}
|
|
|
|
static void ksz9477_get_caps(struct dsa_switch *ds, int port,
|
|
struct phylink_config *config)
|
|
{
|
|
ksz_phylink_get_caps(ds, port, config);
|
|
|
|
config->mac_capabilities = MAC_10 | MAC_100 | MAC_1000FD |
|
|
MAC_ASYM_PAUSE | MAC_SYM_PAUSE;
|
|
}
|
|
|
|
static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
|
|
{
|
|
struct ksz_port *p = &dev->ports[port];
|
|
struct dsa_switch *ds = dev->ds;
|
|
u8 data8, member;
|
|
u16 data16;
|
|
|
|
/* enable tag tail for host port */
|
|
if (cpu_port)
|
|
ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
|
|
true);
|
|
|
|
ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
|
|
|
|
/* set back pressure */
|
|
ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
|
|
|
|
/* enable broadcast storm limit */
|
|
ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
|
|
|
|
/* disable DiffServ priority */
|
|
ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
|
|
|
|
/* replace priority */
|
|
ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
|
|
false);
|
|
ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
|
|
MTI_PVID_REPLACE, false);
|
|
|
|
/* enable 802.1p priority */
|
|
ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
|
|
|
|
if (port < dev->phy_port_cnt) {
|
|
/* do not force flow control */
|
|
ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
|
|
PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
|
|
false);
|
|
|
|
if (dev->info->phy_errata_9477)
|
|
ksz9477_phy_errata_setup(dev, port);
|
|
} else {
|
|
/* force flow control */
|
|
ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
|
|
PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
|
|
true);
|
|
|
|
/* configure MAC to 1G & RGMII mode */
|
|
ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
|
|
switch (p->interface) {
|
|
case PHY_INTERFACE_MODE_MII:
|
|
ksz9477_set_xmii(dev, 0, &data8);
|
|
ksz9477_set_gbit(dev, false, &data8);
|
|
p->phydev.speed = SPEED_100;
|
|
break;
|
|
case PHY_INTERFACE_MODE_RMII:
|
|
ksz9477_set_xmii(dev, 1, &data8);
|
|
ksz9477_set_gbit(dev, false, &data8);
|
|
p->phydev.speed = SPEED_100;
|
|
break;
|
|
case PHY_INTERFACE_MODE_GMII:
|
|
ksz9477_set_xmii(dev, 2, &data8);
|
|
ksz9477_set_gbit(dev, true, &data8);
|
|
p->phydev.speed = SPEED_1000;
|
|
break;
|
|
default:
|
|
ksz9477_set_xmii(dev, 3, &data8);
|
|
ksz9477_set_gbit(dev, true, &data8);
|
|
data8 &= ~PORT_RGMII_ID_IG_ENABLE;
|
|
data8 &= ~PORT_RGMII_ID_EG_ENABLE;
|
|
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
|
p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
|
|
data8 |= PORT_RGMII_ID_IG_ENABLE;
|
|
if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
|
p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
|
|
data8 |= PORT_RGMII_ID_EG_ENABLE;
|
|
/* On KSZ9893, disable RGMII in-band status support */
|
|
if (dev->features & IS_9893)
|
|
data8 &= ~PORT_MII_MAC_MODE;
|
|
p->phydev.speed = SPEED_1000;
|
|
break;
|
|
}
|
|
ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
|
|
p->phydev.duplex = 1;
|
|
}
|
|
|
|
if (cpu_port)
|
|
member = dsa_user_ports(ds);
|
|
else
|
|
member = BIT(dsa_upstream_port(ds, port));
|
|
|
|
ksz9477_cfg_port_member(dev, port, member);
|
|
|
|
/* clear pending interrupts */
|
|
if (port < dev->phy_port_cnt)
|
|
ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
|
|
}
|
|
|
|
static void ksz9477_config_cpu_port(struct dsa_switch *ds)
|
|
{
|
|
struct ksz_device *dev = ds->priv;
|
|
struct ksz_port *p;
|
|
int i;
|
|
|
|
for (i = 0; i < dev->info->port_cnt; i++) {
|
|
if (dsa_is_cpu_port(ds, i) &&
|
|
(dev->info->cpu_ports & (1 << i))) {
|
|
phy_interface_t interface;
|
|
const char *prev_msg;
|
|
const char *prev_mode;
|
|
|
|
dev->cpu_port = i;
|
|
p = &dev->ports[i];
|
|
|
|
/* Read from XMII register to determine host port
|
|
* interface. If set specifically in device tree
|
|
* note the difference to help debugging.
|
|
*/
|
|
interface = ksz9477_get_interface(dev, i);
|
|
if (!p->interface) {
|
|
if (dev->compat_interface) {
|
|
dev_warn(dev->dev,
|
|
"Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
|
|
"Please update your device tree.\n",
|
|
i);
|
|
p->interface = dev->compat_interface;
|
|
} else {
|
|
p->interface = interface;
|
|
}
|
|
}
|
|
if (interface && interface != p->interface) {
|
|
prev_msg = " instead of ";
|
|
prev_mode = phy_modes(interface);
|
|
} else {
|
|
prev_msg = "";
|
|
prev_mode = "";
|
|
}
|
|
dev_info(dev->dev,
|
|
"Port%d: using phy mode %s%s%s\n",
|
|
i,
|
|
phy_modes(p->interface),
|
|
prev_msg,
|
|
prev_mode);
|
|
|
|
/* enable cpu port */
|
|
ksz9477_port_setup(dev, i, true);
|
|
p->on = 1;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < dev->info->port_cnt; i++) {
|
|
if (i == dev->cpu_port)
|
|
continue;
|
|
p = &dev->ports[i];
|
|
|
|
ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED);
|
|
p->on = 1;
|
|
if (i < dev->phy_port_cnt)
|
|
p->phy = 1;
|
|
if (dev->chip_id == 0x00947700 && i == 6) {
|
|
p->sgmii = 1;
|
|
|
|
/* SGMII PHY detection code is not implemented yet. */
|
|
p->phy = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int ksz9477_setup(struct dsa_switch *ds)
|
|
{
|
|
struct ksz_device *dev = ds->priv;
|
|
int ret = 0;
|
|
|
|
dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
|
|
dev->info->num_vlans, GFP_KERNEL);
|
|
if (!dev->vlan_cache)
|
|
return -ENOMEM;
|
|
|
|
ret = ksz9477_reset_switch(dev);
|
|
if (ret) {
|
|
dev_err(ds->dev, "failed to reset switch\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Required for port partitioning. */
|
|
ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
|
|
true);
|
|
|
|
/* Do not work correctly with tail tagging. */
|
|
ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
|
|
|
|
/* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */
|
|
ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true);
|
|
|
|
/* Now we can configure default MTU value */
|
|
ret = regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, REG_SW_MTU_MASK,
|
|
VLAN_ETH_FRAME_LEN + ETH_FCS_LEN);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ksz9477_config_cpu_port(ds);
|
|
|
|
ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
|
|
|
|
/* queue based egress rate limit */
|
|
ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
|
|
|
|
/* enable global MIB counter freeze function */
|
|
ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
|
|
|
|
/* start switch */
|
|
ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
|
|
|
|
ksz_init_mib_timer(dev);
|
|
|
|
ds->configure_vlan_while_not_filtering = false;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dsa_switch_ops ksz9477_switch_ops = {
|
|
.get_tag_protocol = ksz9477_get_tag_protocol,
|
|
.setup = ksz9477_setup,
|
|
.phy_read = ksz9477_phy_read16,
|
|
.phy_write = ksz9477_phy_write16,
|
|
.phylink_mac_link_down = ksz_mac_link_down,
|
|
.phylink_get_caps = ksz9477_get_caps,
|
|
.port_enable = ksz_enable_port,
|
|
.get_strings = ksz_get_strings,
|
|
.get_ethtool_stats = ksz_get_ethtool_stats,
|
|
.get_sset_count = ksz_sset_count,
|
|
.port_bridge_join = ksz_port_bridge_join,
|
|
.port_bridge_leave = ksz_port_bridge_leave,
|
|
.port_stp_state_set = ksz9477_port_stp_state_set,
|
|
.port_fast_age = ksz_port_fast_age,
|
|
.port_vlan_filtering = ksz9477_port_vlan_filtering,
|
|
.port_vlan_add = ksz9477_port_vlan_add,
|
|
.port_vlan_del = ksz9477_port_vlan_del,
|
|
.port_fdb_dump = ksz9477_port_fdb_dump,
|
|
.port_fdb_add = ksz9477_port_fdb_add,
|
|
.port_fdb_del = ksz9477_port_fdb_del,
|
|
.port_mdb_add = ksz9477_port_mdb_add,
|
|
.port_mdb_del = ksz9477_port_mdb_del,
|
|
.port_mirror_add = ksz9477_port_mirror_add,
|
|
.port_mirror_del = ksz9477_port_mirror_del,
|
|
.get_stats64 = ksz_get_stats64,
|
|
.port_change_mtu = ksz9477_change_mtu,
|
|
.port_max_mtu = ksz9477_max_mtu,
|
|
};
|
|
|
|
static u32 ksz9477_get_port_addr(int port, int offset)
|
|
{
|
|
return PORT_CTRL_ADDR(port, offset);
|
|
}
|
|
|
|
static int ksz9477_switch_detect(struct ksz_device *dev)
|
|
{
|
|
u8 data8;
|
|
u8 id_hi;
|
|
u8 id_lo;
|
|
u32 id32;
|
|
int ret;
|
|
|
|
/* turn off SPI DO Edge select */
|
|
ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
|
|
if (ret)
|
|
return ret;
|
|
|
|
data8 &= ~SPI_AUTO_EDGE_DETECTION;
|
|
ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* read chip id */
|
|
ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
|
|
if (ret)
|
|
return ret;
|
|
ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Number of ports can be reduced depending on chip. */
|
|
dev->phy_port_cnt = 5;
|
|
|
|
/* Default capability is gigabit capable. */
|
|
dev->features = GBIT_SUPPORT;
|
|
|
|
dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8);
|
|
id_hi = (u8)(id32 >> 16);
|
|
id_lo = (u8)(id32 >> 8);
|
|
if ((id_lo & 0xf) == 3) {
|
|
/* Chip is from KSZ9893 design. */
|
|
dev_info(dev->dev, "Found KSZ9893\n");
|
|
dev->features |= IS_9893;
|
|
|
|
/* Chip does not support gigabit. */
|
|
if (data8 & SW_QW_ABLE)
|
|
dev->features &= ~GBIT_SUPPORT;
|
|
dev->phy_port_cnt = 2;
|
|
} else {
|
|
dev_info(dev->dev, "Found KSZ9477 or compatible\n");
|
|
/* Chip uses new XMII register definitions. */
|
|
dev->features |= NEW_XMII;
|
|
|
|
/* Chip does not support gigabit. */
|
|
if (!(data8 & SW_GIGABIT_ABLE))
|
|
dev->features &= ~GBIT_SUPPORT;
|
|
}
|
|
|
|
/* Change chip id to known ones so it can be matched against them. */
|
|
id32 = (id_hi << 16) | (id_lo << 8);
|
|
|
|
dev->chip_id = id32;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ksz9477_switch_init(struct ksz_device *dev)
|
|
{
|
|
dev->ds->ops = &ksz9477_switch_ops;
|
|
|
|
dev->port_mask = (1 << dev->info->port_cnt) - 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ksz9477_switch_exit(struct ksz_device *dev)
|
|
{
|
|
ksz9477_reset_switch(dev);
|
|
}
|
|
|
|
static const struct ksz_dev_ops ksz9477_dev_ops = {
|
|
.get_port_addr = ksz9477_get_port_addr,
|
|
.cfg_port_member = ksz9477_cfg_port_member,
|
|
.flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
|
|
.port_setup = ksz9477_port_setup,
|
|
.r_mib_cnt = ksz9477_r_mib_cnt,
|
|
.r_mib_pkt = ksz9477_r_mib_pkt,
|
|
.r_mib_stat64 = ksz_r_mib_stats64,
|
|
.freeze_mib = ksz9477_freeze_mib,
|
|
.port_init_cnt = ksz9477_port_init_cnt,
|
|
.shutdown = ksz9477_reset_switch,
|
|
.detect = ksz9477_switch_detect,
|
|
.init = ksz9477_switch_init,
|
|
.exit = ksz9477_switch_exit,
|
|
};
|
|
|
|
int ksz9477_switch_register(struct ksz_device *dev)
|
|
{
|
|
int ret, i;
|
|
struct phy_device *phydev;
|
|
|
|
ret = ksz_switch_register(dev, &ksz9477_dev_ops);
|
|
if (ret)
|
|
return ret;
|
|
|
|
for (i = 0; i < dev->phy_port_cnt; ++i) {
|
|
if (!dsa_is_user_port(dev->ds, i))
|
|
continue;
|
|
|
|
phydev = dsa_to_port(dev->ds, i)->slave->phydev;
|
|
|
|
/* The MAC actually cannot run in 1000 half-duplex mode. */
|
|
phy_remove_link_mode(phydev,
|
|
ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
|
|
|
|
/* PHY does not support gigabit. */
|
|
if (!(dev->features & GBIT_SUPPORT))
|
|
phy_remove_link_mode(phydev,
|
|
ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
|
|
}
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(ksz9477_switch_register);
|
|
|
|
MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
|
|
MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
|
|
MODULE_LICENSE("GPL");
|