Stephen Boyd 032bcf783e Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next ... - Add Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK - Introduce kstrdup_and_replace() and use it * clk-versa: clk: vc7: Use i2c_get_match_data() instead of device_get_match_data() clk: vc5: Use i2c_get_match_data() instead of device_get_match_data() clk: versaclock3: Switch to use i2c_driver's probe callback clk: Add support for versa3 clock driver dt-bindings: clock: Add Renesas versa3 clock generator bindings * clk-strdup: clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace() clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace() driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace() lib/string_helpers: Add kstrdup_and_replace() helper * clk-amlogic: (22 commits) dt-bindings: soc: amlogic: document System Control registers dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema clk: meson: axg-audio: move bindings include to main driver clk: meson: meson8b: move bindings include to main driver clk: meson: a1: move bindings include to main driver clk: meson: eeclk: move bindings include to main driver clk: meson: aoclk: move bindings include to main driver dt-bindings: clk: axg-audio-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids dt-bindings: clk: meson8b-clkc: expose all clock ids dt-bindings: clk: g12a-aoclkc: expose all clock ids dt-bindings: clk: g12a-clks: expose all clock ids dt-bindings: clk: axg-clkc: expose all clock ids dt-bindings: clk: gxbb-clkc: expose all clock ids clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS ... * clk-allwinner: clk: sunxi-ng: nkm: Prefer current parent rate clk: sunxi-ng: a64: select closest rate for pll-video0 clk: sunxi-ng: div: Support finding closest rate clk: sunxi-ng: mux: Support finding closest rate clk: sunxi-ng: nkm: Support finding closest rate clk: sunxi-ng: nm: Support finding closest rate clk: sunxi-ng: Add helper function to find closest rate clk: sunxi-ng: Add feature to find closest rate clk: sunxi-ng: a64: allow pll-mipi to set parent's rate clk: sunxi-ng: nkm: consider alternative parent rates when determining rate clk: sunxi-ng: nkm: Use correct parameter name for parent HW clk: sunxi-ng: Modify mismatched function name clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource() * clk-rockchip: clk: rockchip: rv1126: Add PD_VO clock tree clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz clk: rockchip: rk3568: Add PLL rate for 101MHz		2023-08-30 14:38:19 -07:00
..
clk-audio-sync.c
clk-bpmp.c	clk: tegra: bpmp: Add a determine_rate hook	2023-06-08 18:39:30 -07:00
clk-device.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
clk-dfll.c	clk: tegra: Don't warn three times about failure to unregister	2023-03-28 19:23:35 -07:00
clk-dfll.h
clk-divider.c
clk-id.h
clk-periph-fixed.c
clk-periph-gate.c	clk: tegra: Don't deassert reset on enabling clocks	2021-05-31 15:16:46 +02:00
clk-periph.c	clk: tegra: periph: Switch to determine_rate	2023-06-08 18:39:35 -07:00
clk-pll-out.c
clk-pll.c	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
clk-sdmmc-mux.c	clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops	2021-07-27 14:54:19 -07:00
clk-super.c	clk: tegra: super: Switch to determine_rate	2023-06-08 18:39:35 -07:00
clk-tegra20-emc.c
clk-tegra20.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
clk-tegra30.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
clk-tegra114.c	clk: tegra: Fix Tegra PWM parent clock	2022-10-14 13:44:24 -07:00
clk-tegra124-dfll-fcpu.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
clk-tegra124-emc.c	clk: tegra: tegra124-emc: Fix potential memory leak	2023-06-14 18:25:51 -07:00
clk-tegra124.c	clk: tegra: Fix Tegra PWM parent clock	2022-10-14 13:44:24 -07:00
clk-tegra210-emc.c
clk-tegra210.c	clk: tegra: Fix Tegra PWM parent clock	2022-10-14 13:44:24 -07:00
clk-tegra-audio.c
clk-tegra-fixed.c
clk-tegra-periph.c	clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock	2021-08-11 11:57:01 +02:00
clk-tegra-super-cclk.c	clk: tegra: Avoid calling an uninitialized function	2023-07-04 08:54:37 -07:00
clk-tegra-super-gen4.c
clk-utils.c
clk.c	Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next	2023-08-30 14:38:19 -07:00
clk.h	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
cvb.c
cvb.h
Kconfig
Makefile	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00