65c9ad77cb
Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
118 lines
3.5 KiB
C
118 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Wendell Lin <wendell.lin@mediatek.com>
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*/
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#include <linux/module.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6779-clk.h>
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static const struct mtk_gate_regs audio0_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x0,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs audio1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x4,
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.sta_ofs = 0x4,
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};
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#define GATE_AUDIO0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
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&mtk_clk_gate_ops_no_setclr)
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#define GATE_AUDIO1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
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&mtk_clk_gate_ops_no_setclr)
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static const struct mtk_gate audio_clks[] = {
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/* AUDIO0 */
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GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
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GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8),
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GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel", 9),
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GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
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"aud_eng2_sel", 18),
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GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner",
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"aud_eng1_sel", 19),
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GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel", 20),
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GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
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GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
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GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
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"audio_sel", 26),
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GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
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GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
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/* AUDIO1 */
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GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk",
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"audio_sel", 4),
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GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk",
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"audio_sel", 5),
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GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk",
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"audio_sel", 6),
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GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk",
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"audio_sel", 7),
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GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk",
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"audio_sel", 8),
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GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s",
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"audio_sel", 12),
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GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1",
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"audio_sel", 13),
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GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2",
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"audio_sel", 14),
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GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires",
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"audio_h_sel", 15),
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GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires",
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"audio_h_sel", 16),
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GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml",
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"audio_h_sel", 17),
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GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc",
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"audio_sel", 20),
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GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
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"audio_h_sel",
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21),
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GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
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28),
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GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
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"audio_sel", 29),
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GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml",
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"audio_sel", 30),
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GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires",
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"audio_h_sel", 31),
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};
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static const struct mtk_clk_desc audio_desc = {
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.clks = audio_clks,
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.num_clks = ARRAY_SIZE(audio_clks),
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};
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static const struct of_device_id of_match_clk_mt6779_aud[] = {
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{
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.compatible = "mediatek,mt6779-audio",
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.data = &audio_desc,
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}, {
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/* sentinel */
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}
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_aud);
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static struct platform_driver clk_mt6779_aud_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt6779-aud",
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.of_match_table = of_match_clk_mt6779_aud,
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},
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};
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module_platform_driver(clk_mt6779_aud_drv);
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MODULE_LICENSE("GPL");
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