Helge Deller 602c9c9a01 parisc: Initialize PCI bridge cache line and default latency
PCI controllers and pci-pci bridges may have not been fully initialized
regarding cache line and defaul latency.

This partly reverts
commit 5f0e9b4 ("parisc: Remove unused pcibios_init_bus()")

Signed-off-by: Helge Deller <deller@gmx.de>
2016-01-12 22:03:21 +01:00
..
2015-11-10 16:32:11 -08:00
2011-03-29 14:48:08 +02:00
2011-03-29 14:48:08 +02:00
2013-04-09 14:13:32 -04:00

/*
** HP VISUALIZE Workstation PCI Bus Defect
**
** "HP has discovered a potential system defect that can affect
** the behavior of five models of HP VISUALIZE workstations when
** equipped with third-party or customer-installed PCI I/O expansion
** cards. The defect is limited to the HP C180, C160, C160L, B160L,
** and B132L VISUALIZE workstations, and will only be encountered
** when data is transmitted through PCI I/O expansion cards on the
** PCI bus. HP-supplied graphics cards that utilize the PCI bus are
** not affected."
**
** http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?locale=en_US&prodTypeId=12454&prodSeriesId=44443
**
**	Product		First Good Serial Number
**  C200/C240 (US)	US67350000
**B132L+/B180 (US)	US67390000
**   C200 (Europe)	3713G01000
**  B180L (Europe)	3720G01000
**
** Note that many boards were fixed/replaced under a free replacement
** program. Assume a machine is only "suspect" until proven otherwise.
**
** "The pci_check program will also be available as application
**  patch PHSS_12295"
*/