Marc Zyngier 674e701270 arm64: Document workaround for Cortex-A72 erratum #853709 ...

We already have a workaround for Cortex-A57 erratum #852523,
but Cortex-A72 r0p0 to r0p2 do suffer from the same issue
(known as erratum #853709).

Let's document the fact that we already handle this.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>

2016-08-17 12:23:47 +02:00

..

debug-sr.c

arm64 updates for 4.6:

2016-03-17 20:03:47 -07:00

entry.S

arm64: KVM: Simplify HYP init/teardown

2016-07-03 23:41:27 +02:00

fpsimd.S

arm64: KVM: Implement fpsimd save/restore

2015-12-14 11:30:41 +00:00

hyp-entry.S

arm64: KVM: Simplify HYP init/teardown

2016-07-03 23:41:27 +02:00

Makefile

arm64: allow building with kcov coverage on ARM64

2016-06-21 16:15:57 +01:00

s2-setup.c

kvm: arm64: Enable hardware updates of the Access Flag for Stage 2 page tables

2016-05-09 22:23:08 +02:00

switch.c

arm64: Document workaround for Cortex-A72 erratum #853709

2016-08-17 12:23:47 +02:00

sysreg-sr.c

arm64: KVM: VHE: Context switch MDSCR_EL1

2016-07-23 18:07:12 +02:00

tlb.c

arm64: KVM: Move kvm/hyp/hyp.h to include/asm/kvm_hyp.h

2016-02-29 18:34:18 +00:00

vgic-v3-sr.c

arm64: KVM: vgic-v3: Relax synchronization when SRE==1

2016-05-31 16:12:17 +02:00