d534fd9787
Infineon S28Hx (SEMPER Octal) and S25FS256T (SEMPER Nano) support Clear Program and Erase Failure Flags (CLPEF, 82h) instead of CLSR(30h). Introduce a new mfr_flag together with the infrastructure to allow manufacturer private data in the core. With this we remove the need to have if checks in the code at runtime and instead set the correct opcodes at probe time. S25Hx (SEMPER QSPI) supports CLSR but it may be disabled by CFR3x[2] while CLPEF is always available. Therefore, the mfr_flag is also applied to S25Hx for safety. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-2-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
250 lines
8.0 KiB
C
250 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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#define WINBOND_NOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
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#define WINBOND_NOR_OP_WREAR 0xc5 /* Write Extended Address Register */
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#define WINBOND_NOR_WREAR_OP(buf) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(WINBOND_NOR_OP_WREAR, 0), \
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SPI_MEM_OP_NO_ADDR, \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_OUT(1, buf, 0))
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static int
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w25q256_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt)
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{
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/*
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* W25Q256JV supports 4B opcodes but W25Q256FV does not.
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* Unfortunately, Winbond has re-used the same JEDEC ID for both
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* variants which prevents us from defining a new entry in the parts
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* table.
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* To differentiate between W25Q256JV and W25Q256FV check SFDP header
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* version: only JV has JESD216A compliant structure (version 5).
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*/
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if (bfpt_header->major == SFDP_JESD216_MAJOR &&
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bfpt_header->minor == SFDP_JESD216A_MINOR)
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nor->flags |= SNOR_F_4B_OPCODES;
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return 0;
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}
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static const struct spi_nor_fixups w25q256_fixups = {
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.post_bfpt = w25q256_post_bfpt_fixups,
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};
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static const struct flash_info winbond_nor_parts[] = {
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/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
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{ "w25x05", INFO(0xef3010, 0, 64 * 1024, 1)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25x10", INFO(0xef3011, 0, 64 * 1024, 2)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25x20", INFO(0xef3012, 0, 64 * 1024, 4)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25x40", INFO(0xef3013, 0, 64 * 1024, 8)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25x80", INFO(0xef3014, 0, 64 * 1024, 16)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25x16", INFO(0xef3015, 0, 64 * 1024, 32)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "w25x32", INFO(0xef3016, 0, 64 * 1024, 64)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25q32", INFO(0xef4016, 0, 64 * 1024, 64)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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OTP_INFO(256, 3, 0x1000, 0x1000) },
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{ "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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OTP_INFO(256, 3, 0x1000, 0x1000) },
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{ "w25q64jwm", INFO(0xef8017, 0, 64 * 1024, 128)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "w25q128jwm", INFO(0xef8018, 0, 64 * 1024, 256)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "w25q256jwm", INFO(0xef8019, 0, 64 * 1024, 512)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "w25q64jvm", INFO(0xef7017, 0, 64 * 1024, 128)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "w25q80", INFO(0xef5014, 0, 64 * 1024, 16)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "w25q128", INFO(0xef4018, 0, 0, 0)
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PARSE_SFDP
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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.fixups = &w25q256_fixups },
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{ "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512)
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PARSE_SFDP },
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{ "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ |
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SPI_NOR_DUAL_READ) },
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{ "w25q512nwq", INFO(0xef6020, 0, 0, 0)
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PARSE_SFDP
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OTP_INFO(256, 3, 0x1000, 0x1000) },
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{ "w25q512nwm", INFO(0xef8020, 0, 64 * 1024, 1024)
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PARSE_SFDP
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OTP_INFO(256, 3, 0x1000, 0x1000) },
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{ "w25q512jvq", INFO(0xef4020, 0, 64 * 1024, 1024)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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};
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/**
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* winbond_nor_write_ear() - Write Extended Address Register.
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* @nor: pointer to 'struct spi_nor'.
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* @ear: value to write to the Extended Address Register.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int winbond_nor_write_ear(struct spi_nor *nor, u8 ear)
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{
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int ret;
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nor->bouncebuf[0] = ear;
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if (nor->spimem) {
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struct spi_mem_op op = WINBOND_NOR_WREAR_OP(nor->bouncebuf);
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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ret = spi_nor_controller_ops_write_reg(nor,
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WINBOND_NOR_OP_WREAR,
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nor->bouncebuf, 1);
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}
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if (ret)
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dev_dbg(nor->dev, "error %d writing EAR\n", ret);
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return ret;
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}
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/**
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* winbond_nor_set_4byte_addr_mode() - Set 4-byte address mode for Winbond
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* flashes.
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* @nor: pointer to 'struct spi_nor'.
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* @enable: true to enter the 4-byte address mode, false to exit the 4-byte
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* address mode.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int winbond_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
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{
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int ret;
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ret = spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable);
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if (ret || enable)
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return ret;
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/*
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* On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address
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* Register to be set to 1, so all 3-byte-address reads come from the
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* second 16M. We must clear the register to enable normal behavior.
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*/
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ret = spi_nor_write_enable(nor);
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if (ret)
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return ret;
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ret = winbond_nor_write_ear(nor, 0);
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if (ret)
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return ret;
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return spi_nor_write_disable(nor);
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}
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static const struct spi_nor_otp_ops winbond_nor_otp_ops = {
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.read = spi_nor_otp_read_secr,
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.write = spi_nor_otp_write_secr,
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.erase = spi_nor_otp_erase_secr,
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.lock = spi_nor_otp_lock_sr2,
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.is_locked = spi_nor_otp_is_locked_sr2,
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};
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static int winbond_nor_late_init(struct spi_nor *nor)
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{
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struct spi_nor_flash_parameter *params = nor->params;
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if (params->otp.org->n_regions)
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params->otp.ops = &winbond_nor_otp_ops;
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/*
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* Winbond seems to require that the Extended Address Register to be set
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* to zero when exiting the 4-Byte Address Mode, at least for W25Q256FV.
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* This requirement is not described in the JESD216 SFDP standard, thus
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* it is Winbond specific. Since we do not know if other Winbond flashes
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* have the same requirement, play safe and overwrite the method parsed
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* from BFPT, if any.
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*/
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params->set_4byte_addr_mode = winbond_nor_set_4byte_addr_mode;
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return 0;
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}
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static const struct spi_nor_fixups winbond_nor_fixups = {
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.late_init = winbond_nor_late_init,
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};
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const struct spi_nor_manufacturer spi_nor_winbond = {
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.name = "winbond",
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.parts = winbond_nor_parts,
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.nparts = ARRAY_SIZE(winbond_nor_parts),
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.fixups = &winbond_nor_fixups,
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};
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