Suzuki K Poulose 67badb2521 arm64: Handle mismatched cache type ...

commit 314d53d297 upstream.

Track mismatches in the cache type register (CTR_EL0), other
than the D/I min line sizes and trap user accesses if there are any.

Fixes: be68a8aaf9 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
Cc: <stable@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2018-09-15 09:43:07 +02:00

..

asm

arm64: Handle mismatched cache type

2018-09-15 09:43:07 +02:00

uapi/asm

arm/arm64: KVM: Add PSCI version selection API

2018-05-09 09:50:19 +02:00