Kishon Vijay Abraham I 6825cfc948 phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz
Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz
as specified in "Common Module Clock Configurations" of the Cadence
Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz
since the only user of Cadence Sierra SERDES, TI J721E SoC provides
input clock frequency of 100MHz. For other frequencies,
cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured
based on the "Common Module Clock Configurations".

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08 12:58:06 +05:30
..
2019-07-01 15:04:59 +02:00
2019-12-05 11:43:31 -08:00