49d576ea72
On MediaTek platforms, CPUXGPT is the source for the AArch64 System
Timer, read through CNTVCT_EL0.
The handling for starting this timer ASAP was introduced in commit
327e93cf9a ("clocksource/drivers/timer-mediatek: Implement CPUXGPT timers")
which description also contains an important full explanation of the
reasons why this driver is necessary and cannot be a module.
In preparation for an eventual conversion of timer-mediatek to a
platform_driver that would be possibly built as a module, split out
the CPUXGPT timers driver to a new timer-mediatek-cpux.c driver.
This commit brings no functional changes.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Walter Chang <walter.chang@mediatek.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230309103913.116775-1-angelogioacchino.delregno@collabora.com
141 lines
3.8 KiB
C
141 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MediaTek SoCs CPUX General Purpose Timer handling
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*
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* Based on timer-mediatek.c:
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* Copyright (C) 2014 Matthias Brugger <matthias.bgg@gmail.com>
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*
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* Copyright (C) 2022 Collabora Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/irqreturn.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#include "timer-of.h"
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#define TIMER_SYNC_TICKS 3
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/* cpux mcusys wrapper */
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#define CPUX_CON_REG 0x0
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#define CPUX_IDX_REG 0x4
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/* cpux */
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#define CPUX_IDX_GLOBAL_CTRL 0x0
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#define CPUX_ENABLE BIT(0)
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#define CPUX_CLK_DIV_MASK GENMASK(10, 8)
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#define CPUX_CLK_DIV1 BIT(8)
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#define CPUX_CLK_DIV2 BIT(9)
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#define CPUX_CLK_DIV4 BIT(10)
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#define CPUX_IDX_GLOBAL_IRQ 0x30
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static u32 mtk_cpux_readl(u32 reg_idx, struct timer_of *to)
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{
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writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
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return readl(timer_of_base(to) + CPUX_CON_REG);
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}
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static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to)
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{
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writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
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writel(val, timer_of_base(to) + CPUX_CON_REG);
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}
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static void mtk_cpux_set_irq(struct timer_of *to, bool enable)
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{
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const unsigned long *irq_mask = cpumask_bits(cpu_possible_mask);
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u32 val;
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val = mtk_cpux_readl(CPUX_IDX_GLOBAL_IRQ, to);
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if (enable)
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val |= *irq_mask;
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else
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val &= ~(*irq_mask);
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mtk_cpux_writel(val, CPUX_IDX_GLOBAL_IRQ, to);
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}
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static int mtk_cpux_clkevt_shutdown(struct clock_event_device *clkevt)
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{
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/* Clear any irq */
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mtk_cpux_set_irq(to_timer_of(clkevt), false);
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/*
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* Disabling CPUXGPT timer will crash the platform, especially
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* if Trusted Firmware is using it (usually, for sleep states),
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* so we only mask the IRQ and call it a day.
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*/
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return 0;
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}
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static int mtk_cpux_clkevt_resume(struct clock_event_device *clkevt)
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{
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mtk_cpux_set_irq(to_timer_of(clkevt), true);
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return 0;
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}
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static struct timer_of to = {
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/*
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* There are per-cpu interrupts for the CPUX General Purpose Timer
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* but since this timer feeds the AArch64 System Timer we can rely
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* on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ.
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*/
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.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
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.clkevt = {
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.name = "mtk-cpuxgpt",
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.cpumask = cpu_possible_mask,
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.rating = 10,
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.set_state_shutdown = mtk_cpux_clkevt_shutdown,
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.tick_resume = mtk_cpux_clkevt_resume,
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},
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};
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static int __init mtk_cpux_init(struct device_node *node)
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{
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u32 freq, val;
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int ret;
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/* If this fails, bad things are about to happen... */
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ret = timer_of_init(node, &to);
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if (ret) {
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WARN(1, "Cannot start CPUX timers.\n");
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return ret;
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}
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/*
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* Check if we're given a clock with the right frequency for this
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* timer, otherwise warn but keep going with the setup anyway, as
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* that makes it possible to still boot the kernel, even though
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* it may not work correctly (random lockups, etc).
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* The reason behind this is that having an early UART may not be
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* possible for everyone and this gives a chance to retrieve kmsg
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* for eventual debugging even on consumer devices.
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*/
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freq = timer_of_rate(&to);
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if (freq > 13000000)
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WARN(1, "Requested unsupported timer frequency %u\n", freq);
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/* Clock input is 26MHz, set DIV2 to achieve 13MHz clock */
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val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to);
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val &= ~CPUX_CLK_DIV_MASK;
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val |= CPUX_CLK_DIV2;
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mtk_cpux_writel(val, CPUX_IDX_GLOBAL_CTRL, &to);
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/* Enable all CPUXGPT timers */
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val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to);
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mtk_cpux_writel(val | CPUX_ENABLE, CPUX_IDX_GLOBAL_CTRL, &to);
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clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
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TIMER_SYNC_TICKS, 0xffffffff);
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return 0;
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}
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TIMER_OF_DECLARE(mtk_mt6795, "mediatek,mt6795-systimer", mtk_cpux_init);
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