48c1c40ab4
There are a couple of subsystems maintained by other people that merge their drivers through the SoC tree, those changes include: - The SCMI firmware framework gains support for sensor notifications and for controlling voltage domains. - A large update for the Tegra memory controller driver, integrating it better with the interconnect framework - The memory controller subsystem gains support for Mediatek MT8192 - The reset controller framework gains support for sharing pulsed resets For Soc specific drivers in drivers/soc, the main changes are - The Allwinner/sunxi MBUS gets a rework for the way it handles dma_map_ops and offsets between physical and dma address spaces. - An errata fix plus some cleanups for Freescale Layerscape SoCs - A cleanup for renesas drivers regarding MMIO accesses. - New SoC specific drivers for Mediatek MT8192 and MT8183 power domains - New SoC specific drivers for Aspeed AST2600 LPC bus control and SoC identification. - Core Power Domain support for Qualcomm MSM8916, MSM8939, SDM660 and SDX55. - A rework of the TI AM33xx 'genpd' power domain support to use information from DT instead of platform data - Support for TI AM64x SoCs - Allow building some Amlogic drivers as modules instead of built-in Finally, there are numerous cleanups and smaller bug fixes for Mediatek, Tegra, Samsung, Qualcomm, TI OMAP, Amlogic, Rockchips, Renesas, and Xilinx SoCs. There is a trivial conflict in the cedrus driver, with two branches adding the same CEDRUS_CAPABILITY_H265_DEC flag, and another trivial remove/remove conflict in linux/dma-mapping.h. Signed-off-by: Arnd Bergmann <arnd@arndb.de> -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAl/alSUACgkQmmx57+YA GNm7GRAAlNMVi7F0f4Ixf1bEh+J2QUonYIpZfrdxOLFwISGQ+nstGrFW2He/OeQv KAi027tZLl6Sdzjy809cLDPA4Z2IKwjVWhEbBHybvy1+irPYjnixtLd0x3YvPhjH iadlcjQ3uaGue8PvubK6CVnBEy82A+Pp29n9i4A4wX/8w+BVIhVsxwQWUBF8pFXE 3La2UZYZMVMvVZMrpTOqwCgdmLDCk+RLMVZ1IiRqBEBq5/DVq03uIXgjGEOrq8tl PXC89w7K510Is891mbBdBThQf+pZkU1vwORuknDcEJKWs9ngbEha7ebVgp32kbFl pi8DEK205d106WQgfn0Zxkpbsp8XD058wDILwkhBcteXlBaUEL6btGVLDTUCJZuv /pkH8tL4lNGpThQFbCEXC8oHZBp2xk55P+SW9RRZOoA5tAp+sz7hlf3y3YKdCSxv 4xybeeVOAgjl01WtbEC7CuIkqcKVSQ7njhLhC8r5ASteNywDThqxLT6nd0VegcQc YH3Eu9QRXpvFwQ35zMkTMWa27bMG5d60fp90bWT0R5amXZpxJJot87w8trFCxv74 mE5KvCbefCRNsTt8GOBA/WR7hVaG369g07qOvs7g4LjJEM3Nl2h/A4/zVFef9O0t yq3Nm4YCGfDSAQXzGR2SJ3nxiqbDknzJTAtZPf4BmbaMuPOIJ5k= =BjJf -----END PGP SIGNATURE----- Merge tag 'arm-soc-drivers-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "There are a couple of subsystems maintained by other people that merge their drivers through the SoC tree, those changes include: - The SCMI firmware framework gains support for sensor notifications and for controlling voltage domains. - A large update for the Tegra memory controller driver, integrating it better with the interconnect framework - The memory controller subsystem gains support for Mediatek MT8192 - The reset controller framework gains support for sharing pulsed resets For Soc specific drivers in drivers/soc, the main changes are - The Allwinner/sunxi MBUS gets a rework for the way it handles dma_map_ops and offsets between physical and dma address spaces. - An errata fix plus some cleanups for Freescale Layerscape SoCs - A cleanup for renesas drivers regarding MMIO accesses. - New SoC specific drivers for Mediatek MT8192 and MT8183 power domains - New SoC specific drivers for Aspeed AST2600 LPC bus control and SoC identification. - Core Power Domain support for Qualcomm MSM8916, MSM8939, SDM660 and SDX55. - A rework of the TI AM33xx 'genpd' power domain support to use information from DT instead of platform data - Support for TI AM64x SoCs - Allow building some Amlogic drivers as modules instead of built-in Finally, there are numerous cleanups and smaller bug fixes for Mediatek, Tegra, Samsung, Qualcomm, TI OMAP, Amlogic, Rockchips, Renesas, and Xilinx SoCs" * tag 'arm-soc-drivers-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (222 commits) soc: mediatek: mmsys: Specify HAS_IOMEM dependency for MTK_MMSYS firmware: xilinx: Properly align function parameter firmware: xilinx: Add a blank line after function declaration firmware: xilinx: Remove additional newline firmware: xilinx: Fix kernel-doc warnings firmware: xlnx-zynqmp: fix compilation warning soc: xilinx: vcu: add missing register NUM_CORE soc: xilinx: vcu: use vcu-settings syscon registers dt-bindings: soc: xlnx: extract xlnx, vcu-settings to separate binding soc: xilinx: vcu: drop useless success message clk: samsung: mark PM functions as __maybe_unused soc: samsung: exynos-chipid: initialize later - with arch_initcall soc: samsung: exynos-chipid: order list of SoCs by name memory: jz4780_nemc: Fix potential NULL dereference in jz4780_nemc_probe() memory: ti-emif-sram: only build for ARMv7 memory: tegra30: Support interconnect framework memory: tegra20: Support hardware versioning and clean up OPP table initialization dt-bindings: memory: tegra20-emc: Document opp-supported-hw property soc: rockchip: io-domain: Fix error return code in rockchip_iodomain_probe() reset-controller: ti: force the write operation when assert or deassert ...
261 lines
7.8 KiB
Plaintext
261 lines
7.8 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
config ARCH_HAS_RESET_CONTROLLER
|
|
bool
|
|
|
|
menuconfig RESET_CONTROLLER
|
|
bool "Reset Controller Support"
|
|
default y if ARCH_HAS_RESET_CONTROLLER
|
|
help
|
|
Generic Reset Controller support.
|
|
|
|
This framework is designed to abstract reset handling of devices
|
|
via GPIOs or SoC-internal reset controller modules.
|
|
|
|
If unsure, say no.
|
|
|
|
if RESET_CONTROLLER
|
|
|
|
config RESET_A10SR
|
|
tristate "Altera Arria10 System Resource Reset"
|
|
depends on MFD_ALTERA_A10SR
|
|
help
|
|
This option enables support for the external reset functions for
|
|
peripheral PHYs on the Altera Arria10 System Resource Chip.
|
|
|
|
config RESET_ATH79
|
|
bool "AR71xx Reset Driver" if COMPILE_TEST
|
|
default ATH79
|
|
help
|
|
This enables the ATH79 reset controller driver that supports the
|
|
AR71xx SoC reset controller.
|
|
|
|
config RESET_AXS10X
|
|
bool "AXS10x Reset Driver" if COMPILE_TEST
|
|
default ARC_PLAT_AXS10X
|
|
help
|
|
This enables the reset controller driver for AXS10x.
|
|
|
|
config RESET_BCM6345
|
|
bool "BCM6345 Reset Controller"
|
|
depends on BMIPS_GENERIC || COMPILE_TEST
|
|
default BMIPS_GENERIC
|
|
help
|
|
This enables the reset controller driver for BCM6345 SoCs.
|
|
|
|
config RESET_BERLIN
|
|
bool "Berlin Reset Driver" if COMPILE_TEST
|
|
default ARCH_BERLIN
|
|
help
|
|
This enables the reset controller driver for Marvell Berlin SoCs.
|
|
|
|
config RESET_BRCMSTB
|
|
tristate "Broadcom STB reset controller"
|
|
depends on ARCH_BRCMSTB || COMPILE_TEST
|
|
default ARCH_BRCMSTB
|
|
help
|
|
This enables the reset controller driver for Broadcom STB SoCs using
|
|
a SUN_TOP_CTRL_SW_INIT style controller.
|
|
|
|
config RESET_BRCMSTB_RESCAL
|
|
bool "Broadcom STB RESCAL reset controller"
|
|
depends on HAS_IOMEM
|
|
default ARCH_BRCMSTB || COMPILE_TEST
|
|
help
|
|
This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
|
|
BCM7216.
|
|
|
|
config RESET_HSDK
|
|
bool "Synopsys HSDK Reset Driver"
|
|
depends on HAS_IOMEM
|
|
depends on ARC_SOC_HSDK || COMPILE_TEST
|
|
help
|
|
This enables the reset controller driver for HSDK board.
|
|
|
|
config RESET_IMX7
|
|
tristate "i.MX7/8 Reset Driver"
|
|
depends on HAS_IOMEM
|
|
depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
|
|
default y if SOC_IMX7D
|
|
select MFD_SYSCON
|
|
help
|
|
This enables the reset controller driver for i.MX7 SoCs.
|
|
|
|
config RESET_INTEL_GW
|
|
bool "Intel Reset Controller Driver"
|
|
depends on OF && HAS_IOMEM
|
|
select REGMAP_MMIO
|
|
help
|
|
This enables the reset controller driver for Intel Gateway SoCs.
|
|
Say Y to control the reset signals provided by reset controller.
|
|
Otherwise, say N.
|
|
|
|
config RESET_LANTIQ
|
|
bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
|
|
default SOC_TYPE_XWAY
|
|
help
|
|
This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
|
|
|
|
config RESET_LPC18XX
|
|
bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
|
|
default ARCH_LPC18XX
|
|
help
|
|
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
|
|
|
|
config RESET_MESON
|
|
tristate "Meson Reset Driver"
|
|
depends on ARCH_MESON || COMPILE_TEST
|
|
default ARCH_MESON
|
|
help
|
|
This enables the reset driver for Amlogic Meson SoCs.
|
|
|
|
config RESET_MESON_AUDIO_ARB
|
|
tristate "Meson Audio Memory Arbiter Reset Driver"
|
|
depends on ARCH_MESON || COMPILE_TEST
|
|
help
|
|
This enables the reset driver for Audio Memory Arbiter of
|
|
Amlogic's A113 based SoCs
|
|
|
|
config RESET_NPCM
|
|
bool "NPCM BMC Reset Driver" if COMPILE_TEST
|
|
default ARCH_NPCM
|
|
help
|
|
This enables the reset controller driver for Nuvoton NPCM
|
|
BMC SoCs.
|
|
|
|
config RESET_OXNAS
|
|
bool
|
|
|
|
config RESET_PISTACHIO
|
|
bool "Pistachio Reset Driver" if COMPILE_TEST
|
|
default MACH_PISTACHIO
|
|
help
|
|
This enables the reset driver for ImgTec Pistachio SoCs.
|
|
|
|
config RESET_QCOM_AOSS
|
|
tristate "Qcom AOSS Reset Driver"
|
|
depends on ARCH_QCOM || COMPILE_TEST
|
|
help
|
|
This enables the AOSS (always on subsystem) reset driver
|
|
for Qualcomm SDM845 SoCs. Say Y if you want to control
|
|
reset signals provided by AOSS for Modem, Venus, ADSP,
|
|
GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
|
|
|
|
config RESET_QCOM_PDC
|
|
tristate "Qualcomm PDC Reset Driver"
|
|
depends on ARCH_QCOM || COMPILE_TEST
|
|
help
|
|
This enables the PDC (Power Domain Controller) reset driver
|
|
for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
|
|
to control reset signals provided by PDC for Modem, Compute,
|
|
Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
|
|
|
|
config RESET_RASPBERRYPI
|
|
tristate "Raspberry Pi 4 Firmware Reset Driver"
|
|
depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
|
|
default USB_XHCI_PCI
|
|
help
|
|
Raspberry Pi 4's co-processor controls some of the board's HW
|
|
initialization process, but it's up to Linux to trigger it when
|
|
relevant. This driver provides a reset controller capable of
|
|
interfacing with RPi4's co-processor and model these firmware
|
|
initialization routines as reset lines.
|
|
|
|
config RESET_SCMI
|
|
tristate "Reset driver controlled via ARM SCMI interface"
|
|
depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
|
|
default ARM_SCMI_PROTOCOL
|
|
help
|
|
This driver provides support for reset signal/domains that are
|
|
controlled by firmware that implements the SCMI interface.
|
|
|
|
This driver uses SCMI Message Protocol to interact with the
|
|
firmware controlling all the reset signals.
|
|
|
|
config RESET_SIMPLE
|
|
bool "Simple Reset Controller Driver" if COMPILE_TEST
|
|
default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
|
|
help
|
|
This enables a simple reset controller driver for reset lines that
|
|
that can be asserted and deasserted by toggling bits in a contiguous,
|
|
exclusive register space.
|
|
|
|
Currently this driver supports:
|
|
- Altera SoCFPGAs
|
|
- ASPEED BMC SoCs
|
|
- Bitmain BM1880 SoC
|
|
- Realtek SoCs
|
|
- RCC reset controller in STM32 MCUs
|
|
- Allwinner SoCs
|
|
- ZTE's zx2967 family
|
|
|
|
config RESET_STM32MP157
|
|
bool "STM32MP157 Reset Driver" if COMPILE_TEST
|
|
default MACH_STM32MP157
|
|
help
|
|
This enables the RCC reset controller driver for STM32 MPUs.
|
|
|
|
config RESET_SOCFPGA
|
|
bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
|
|
default ARCH_SOCFPGA
|
|
select RESET_SIMPLE
|
|
help
|
|
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
|
|
driver gets initialized early during platform init calls.
|
|
|
|
config RESET_SUNXI
|
|
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
|
|
default ARCH_SUNXI
|
|
select RESET_SIMPLE
|
|
help
|
|
This enables the reset driver for Allwinner SoCs.
|
|
|
|
config RESET_TI_SCI
|
|
tristate "TI System Control Interface (TI-SCI) reset driver"
|
|
depends on TI_SCI_PROTOCOL
|
|
help
|
|
This enables the reset driver support over TI System Control Interface
|
|
available on some new TI's SoCs. If you wish to use reset resources
|
|
managed by the TI System Controller, say Y here. Otherwise, say N.
|
|
|
|
config RESET_TI_SYSCON
|
|
tristate "TI SYSCON Reset Driver"
|
|
depends on HAS_IOMEM
|
|
select MFD_SYSCON
|
|
help
|
|
This enables the reset driver support for TI devices with
|
|
memory-mapped reset registers as part of a syscon device node. If
|
|
you wish to use the reset framework for such memory-mapped devices,
|
|
say Y here. Otherwise, say N.
|
|
|
|
config RESET_UNIPHIER
|
|
tristate "Reset controller driver for UniPhier SoCs"
|
|
depends on ARCH_UNIPHIER || COMPILE_TEST
|
|
depends on OF && MFD_SYSCON
|
|
default ARCH_UNIPHIER
|
|
help
|
|
Support for reset controllers on UniPhier SoCs.
|
|
Say Y if you want to control reset signals provided by System Control
|
|
block, Media I/O block, Peripheral Block.
|
|
|
|
config RESET_UNIPHIER_GLUE
|
|
tristate "Reset driver in glue layer for UniPhier SoCs"
|
|
depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
|
|
default ARCH_UNIPHIER
|
|
select RESET_SIMPLE
|
|
help
|
|
Support for peripheral core reset included in its own glue layer
|
|
on UniPhier SoCs. Say Y if you want to control reset signals
|
|
provided by the glue layer.
|
|
|
|
config RESET_ZYNQ
|
|
bool "ZYNQ Reset Driver" if COMPILE_TEST
|
|
default ARCH_ZYNQ
|
|
help
|
|
This enables the reset controller driver for Xilinx Zynq SoCs.
|
|
|
|
source "drivers/reset/sti/Kconfig"
|
|
source "drivers/reset/hisilicon/Kconfig"
|
|
source "drivers/reset/tegra/Kconfig"
|
|
|
|
endif
|