Felix Fietkau 6b42e8d03b ath9k_hw: fix fast clock handling for 5GHz channels
Combine multiple checks that were supposed to check for the same
conditions, but didn't. Always enable fast PLL clock on AR9280 2.0

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-04-27 16:09:18 -04:00
..
2010-04-20 11:50:52 -04:00
2009-10-07 16:39:29 -04:00
2010-03-23 16:50:17 -04:00
2010-03-23 16:50:17 -04:00
2009-10-07 16:39:41 -04:00
2009-10-07 16:39:28 -04:00
2010-04-06 16:51:04 -04:00