b41e38e225
This adds the support for IOMMU_HWPT_DATA_VTD_S1 type. And 'nested_parent' is added to mark the nested parent domain to sanitize the input parent domain. Link: https://lore.kernel.org/r/20231026044216.64964-8-yi.l.liu@intel.com Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Yi Liu <yi.l.liu@intel.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* nested.c - nested mode translation support
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*
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* Copyright (C) 2023 Intel Corporation
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*
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* Author: Lu Baolu <baolu.lu@linux.intel.com>
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* Jacob Pan <jacob.jun.pan@linux.intel.com>
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* Yi Liu <yi.l.liu@intel.com>
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*/
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#define pr_fmt(fmt) "DMAR: " fmt
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#include <linux/iommu.h>
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#include <linux/pci.h>
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#include <linux/pci-ats.h>
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#include "iommu.h"
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#include "pasid.h"
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static int intel_nested_attach_dev(struct iommu_domain *domain,
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struct device *dev)
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{
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struct device_domain_info *info = dev_iommu_priv_get(dev);
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struct dmar_domain *dmar_domain = to_dmar_domain(domain);
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struct intel_iommu *iommu = info->iommu;
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unsigned long flags;
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int ret = 0;
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if (info->domain)
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device_block_translation(dev);
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if (iommu->agaw < dmar_domain->s2_domain->agaw) {
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dev_err_ratelimited(dev, "Adjusted guest address width not compatible\n");
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return -ENODEV;
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}
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/*
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* Stage-1 domain cannot work alone, it is nested on a s2_domain.
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* The s2_domain will be used in nested translation, hence needs
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* to ensure the s2_domain is compatible with this IOMMU.
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*/
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ret = prepare_domain_attach_device(&dmar_domain->s2_domain->domain, dev);
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if (ret) {
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dev_err_ratelimited(dev, "s2 domain is not compatible\n");
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return ret;
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}
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ret = domain_attach_iommu(dmar_domain, iommu);
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if (ret) {
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dev_err_ratelimited(dev, "Failed to attach domain to iommu\n");
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return ret;
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}
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ret = intel_pasid_setup_nested(iommu, dev,
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IOMMU_NO_PASID, dmar_domain);
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if (ret) {
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domain_detach_iommu(dmar_domain, iommu);
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dev_err_ratelimited(dev, "Failed to setup pasid entry\n");
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return ret;
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}
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info->domain = dmar_domain;
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spin_lock_irqsave(&dmar_domain->lock, flags);
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list_add(&info->link, &dmar_domain->devices);
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spin_unlock_irqrestore(&dmar_domain->lock, flags);
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return 0;
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}
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static void intel_nested_domain_free(struct iommu_domain *domain)
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{
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kfree(to_dmar_domain(domain));
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}
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static const struct iommu_domain_ops intel_nested_domain_ops = {
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.attach_dev = intel_nested_attach_dev,
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.free = intel_nested_domain_free,
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};
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struct iommu_domain *intel_nested_domain_alloc(struct iommu_domain *parent,
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const struct iommu_user_data *user_data)
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{
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struct dmar_domain *s2_domain = to_dmar_domain(parent);
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struct iommu_hwpt_vtd_s1 vtd;
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struct dmar_domain *domain;
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int ret;
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/* Must be nested domain */
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if (user_data->type != IOMMU_HWPT_DATA_VTD_S1)
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return ERR_PTR(-EOPNOTSUPP);
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if (parent->ops != intel_iommu_ops.default_domain_ops ||
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!s2_domain->nested_parent)
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return ERR_PTR(-EINVAL);
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ret = iommu_copy_struct_from_user(&vtd, user_data,
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IOMMU_HWPT_DATA_VTD_S1, __reserved);
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if (ret)
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return ERR_PTR(ret);
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domain = kzalloc(sizeof(*domain), GFP_KERNEL_ACCOUNT);
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if (!domain)
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return ERR_PTR(-ENOMEM);
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domain->use_first_level = true;
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domain->s2_domain = s2_domain;
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domain->s1_pgtbl = vtd.pgtbl_addr;
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domain->s1_cfg = vtd;
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domain->domain.ops = &intel_nested_domain_ops;
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domain->domain.type = IOMMU_DOMAIN_NESTED;
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INIT_LIST_HEAD(&domain->devices);
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INIT_LIST_HEAD(&domain->dev_pasids);
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spin_lock_init(&domain->lock);
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xa_init(&domain->iommu_array);
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return &domain->domain;
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}
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