Vincent Chen 6d1a6f464e

rseq/selftests: Add support for RISC-V ...

Add support for RISC-V in the rseq selftests, which covers both
64-bit and 32-bit ISA with little endian mode.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Tested-by: Eric Lin <eric.lin@sifive.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

2022-03-22 14:45:19 -07:00

..

.gitignore

.gitignore: add SPDX License Identifier

2020-03-25 11:50:48 +01:00

basic_percpu_ops_test.c

selftests/rseq: remove ARRAY_SIZE define from individual tests

2021-12-10 17:51:03 -07:00

basic_test.c

…

Makefile

selftests/rseq: Fix out-of-tree compilation

2020-02-20 08:57:12 -07:00

param_test.c

rseq/selftests: Add support for RISC-V

2022-03-22 14:45:19 -07:00

rseq-arm64.h

rseq/selftests: aarch64 code signature: handle big-endian environment

2019-05-07 15:32:51 -06:00

rseq-arm.h

rseq/selftests: Fix Thumb mode build failure on arm32

2019-07-08 13:00:41 -06:00

rseq-mips.h

rseq/selftests: mips: use break instruction for RSEQ_SIG

2019-05-07 15:33:09 -06:00

rseq-ppc.h

rseq/selftests: powerpc code signature: generate valid instructions

2019-05-07 15:33:00 -06:00

rseq-riscv.h

rseq/selftests: Add support for RISC-V

2022-03-22 14:45:19 -07:00

rseq-s390.h

linux-kselftest-5.2-rc1-2

2019-05-16 18:57:58 -07:00

rseq-skip.h

…

rseq-x86.h

rseq/selftests,x86_64: Add rseq_offset_deref_addv()

2020-09-25 14:23:27 +02:00

rseq.c

selftests/rseq: remove ARRAY_SIZE define from individual tests

2021-12-10 17:51:03 -07:00

rseq.h

rseq/selftests: Add support for RISC-V

2022-03-22 14:45:19 -07:00

run_param_test.sh

rseq/selftests: Test MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ

2020-09-25 14:23:27 +02:00

settings

rseq/selftests: Turn off timeout setting

2019-12-23 10:52:41 -07:00