4d352eb91a
We will use the infra_ao reset which is defined in mt8192-sys-clock and mt8195-sys-clock. The value of reset-cells is 1. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-13-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
69 lines
1.5 KiB
YAML
69 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: MediaTek System Clock Controller for MT8192
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maintainers:
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
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description:
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The Mediatek system clock controller provides various clocks and system configuration
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like reset and bus protection on MT8192.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8192-topckgen
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- mediatek,mt8192-infracfg
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- mediatek,mt8192-pericfg
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- mediatek,mt8192-apmixedsys
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt8192-topckgen", "syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt8192-infracfg", "syscon";
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reg = <0x10001000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt8192-pericfg", "syscon";
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reg = <0x10003000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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apmixedsys: syscon@1000c000 {
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compatible = "mediatek,mt8192-apmixedsys", "syscon";
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reg = <0x1000c000 0x1000>;
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#clock-cells = <1>;
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};
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