6dbd682b7c
This patch implements supports for EHCI controllers whose in-memory data structures are represented in big-endian format. This is needed (unfortunately) for the AMCC PPC440EPx SoC EHCI controller; the EHCI spec doesn't specify little-endian format, although that's what most other implementations use. The guts of the patch are to introduce the hc32 type and change all references from le32 to hc32. All access routines are converted from cpu_to_le32(...) to cpu_to_hc32(ehci, ...) and similar for the other "direction". (This is the same approach used with OHCI.) David fixed: Whitespace fixes; refresh against ehci cpufreq patch; move glue for that PPC driver to the patch adding it; fix free symbol capture bugs in modified "constant" macros; and make "hc32" etc be "le32" unless we really need the BE options, so "sparse" can do some real good. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
236 lines
6.2 KiB
C
236 lines
6.2 KiB
C
/*
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* Copyright (c) 2001 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* this file is part of ehci-hcd.c */
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/*-------------------------------------------------------------------------*/
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/*
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* There's basically three types of memory:
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* - data used only by the HCD ... kmalloc is fine
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* - async and periodic schedules, shared by HC and HCD ... these
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* need to use dma_pool or dma_alloc_coherent
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* - driver buffers, read/written by HC ... single shot DMA mapped
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*
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* There's also "register" data (e.g. PCI or SOC), which is memory mapped.
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* No memory seen by this driver is pageable.
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*/
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/*-------------------------------------------------------------------------*/
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/* Allocate the key transfer structures from the previously allocated pool */
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static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
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dma_addr_t dma)
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{
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memset (qtd, 0, sizeof *qtd);
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qtd->qtd_dma = dma;
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qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
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qtd->hw_next = EHCI_LIST_END(ehci);
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qtd->hw_alt_next = EHCI_LIST_END(ehci);
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INIT_LIST_HEAD (&qtd->qtd_list);
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}
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static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
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{
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struct ehci_qtd *qtd;
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dma_addr_t dma;
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qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
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if (qtd != NULL) {
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ehci_qtd_init(ehci, qtd, dma);
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}
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return qtd;
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}
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static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
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{
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dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
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}
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static void qh_destroy (struct kref *kref)
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{
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struct ehci_qh *qh = container_of(kref, struct ehci_qh, kref);
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struct ehci_hcd *ehci = qh->ehci;
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/* clean qtds first, and know this is not linked */
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if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
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ehci_dbg (ehci, "unused qh not empty!\n");
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BUG ();
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}
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if (qh->dummy)
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ehci_qtd_free (ehci, qh->dummy);
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dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
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}
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static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
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{
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struct ehci_qh *qh;
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dma_addr_t dma;
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qh = (struct ehci_qh *)
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dma_pool_alloc (ehci->qh_pool, flags, &dma);
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if (!qh)
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return qh;
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memset (qh, 0, sizeof *qh);
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kref_init(&qh->kref);
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qh->ehci = ehci;
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qh->qh_dma = dma;
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// INIT_LIST_HEAD (&qh->qh_list);
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INIT_LIST_HEAD (&qh->qtd_list);
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#ifdef CONFIG_CPU_FREQ
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INIT_LIST_HEAD (&qh->split_intr_qhs);
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#endif
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/* dummy td enables safe urb queuing */
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qh->dummy = ehci_qtd_alloc (ehci, flags);
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if (qh->dummy == NULL) {
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ehci_dbg (ehci, "no dummy td\n");
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dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
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qh = NULL;
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}
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return qh;
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}
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/* to share a qh (cpu threads, or hc) */
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static inline struct ehci_qh *qh_get (struct ehci_qh *qh)
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{
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kref_get(&qh->kref);
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return qh;
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}
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static inline void qh_put (struct ehci_qh *qh)
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{
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kref_put(&qh->kref, qh_destroy);
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}
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/*-------------------------------------------------------------------------*/
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/* The queue heads and transfer descriptors are managed from pools tied
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* to each of the "per device" structures.
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* This is the initialisation and cleanup code.
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*/
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static void ehci_mem_cleanup (struct ehci_hcd *ehci)
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{
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if (ehci->async)
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qh_put (ehci->async);
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ehci->async = NULL;
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/* DMA consistent memory and pools */
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if (ehci->qtd_pool)
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dma_pool_destroy (ehci->qtd_pool);
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ehci->qtd_pool = NULL;
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if (ehci->qh_pool) {
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dma_pool_destroy (ehci->qh_pool);
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ehci->qh_pool = NULL;
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}
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if (ehci->itd_pool)
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dma_pool_destroy (ehci->itd_pool);
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ehci->itd_pool = NULL;
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if (ehci->sitd_pool)
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dma_pool_destroy (ehci->sitd_pool);
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ehci->sitd_pool = NULL;
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if (ehci->periodic)
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dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
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ehci->periodic_size * sizeof (u32),
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ehci->periodic, ehci->periodic_dma);
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ehci->periodic = NULL;
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/* shadow periodic table */
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kfree(ehci->pshadow);
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ehci->pshadow = NULL;
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}
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/* remember to add cleanup code (above) if you add anything here */
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static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
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{
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int i;
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/* QTDs for control/bulk/intr transfers */
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ehci->qtd_pool = dma_pool_create ("ehci_qtd",
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ehci_to_hcd(ehci)->self.controller,
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sizeof (struct ehci_qtd),
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32 /* byte alignment (for hw parts) */,
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4096 /* can't cross 4K */);
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if (!ehci->qtd_pool) {
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goto fail;
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}
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/* QHs for control/bulk/intr transfers */
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ehci->qh_pool = dma_pool_create ("ehci_qh",
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ehci_to_hcd(ehci)->self.controller,
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sizeof (struct ehci_qh),
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32 /* byte alignment (for hw parts) */,
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4096 /* can't cross 4K */);
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if (!ehci->qh_pool) {
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goto fail;
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}
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ehci->async = ehci_qh_alloc (ehci, flags);
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if (!ehci->async) {
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goto fail;
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}
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/* ITD for high speed ISO transfers */
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ehci->itd_pool = dma_pool_create ("ehci_itd",
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ehci_to_hcd(ehci)->self.controller,
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sizeof (struct ehci_itd),
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32 /* byte alignment (for hw parts) */,
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4096 /* can't cross 4K */);
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if (!ehci->itd_pool) {
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goto fail;
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}
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/* SITD for full/low speed split ISO transfers */
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ehci->sitd_pool = dma_pool_create ("ehci_sitd",
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ehci_to_hcd(ehci)->self.controller,
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sizeof (struct ehci_sitd),
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32 /* byte alignment (for hw parts) */,
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4096 /* can't cross 4K */);
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if (!ehci->sitd_pool) {
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goto fail;
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}
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/* Hardware periodic table */
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ehci->periodic = (__le32 *)
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dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
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ehci->periodic_size * sizeof(__le32),
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&ehci->periodic_dma, 0);
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if (ehci->periodic == NULL) {
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goto fail;
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}
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for (i = 0; i < ehci->periodic_size; i++)
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ehci->periodic [i] = EHCI_LIST_END(ehci);
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/* software shadow of hardware table */
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ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
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if (ehci->pshadow != NULL)
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return 0;
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fail:
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ehci_dbg (ehci, "couldn't init memory\n");
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ehci_mem_cleanup (ehci);
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return -ENOMEM;
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}
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