7cf4cc3e85
The SPEAr320s SOC is a SPEAr320 SOC variant. Mostly identical to the SPEAr320 SOC variant, it has a new interrupt routing for PL_PGIOs. Add spear320s.dtsi to handle SPEAr320s SOC Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20211202095255.165797-7-herve.codina@bootlin.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
25 lines
450 B
Plaintext
25 lines
450 B
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* DTS file for SPEAr320s SoC
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*
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* Copyright 2021 Herve Codina <herve.codina@bootlin.com>
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*/
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/include/ "spear320.dtsi"
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/ {
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ahb {
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apb {
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gpiopinctrl: gpio@b3000000 {
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/*
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* The "RM0321 SPEAr320s address and map
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* registers" document mentions interrupt 6
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* (NPGIO_INTR) for the PL_GPIO interrupt.
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*/
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interrupts = <6>;
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interrupt-parent = <&shirq>;
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};
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};
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};
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};
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