7a6fca879f
On the A80 SoC, the 4 mmc controllers each have a separate register controlling their register access clocks and reset controls. These registers in turn share a ahb clock gate and reset control. This patch adds a platform device driver for these controls. It requires both clocks and reset controls to be available, so using CLK_OF_DECLARE might not be the best way. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
16 lines
333 B
Makefile
16 lines
333 B
Makefile
#
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# Makefile for sunxi specific clk
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#
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obj-y += clk-sunxi.o clk-factors.o
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obj-y += clk-a10-hosc.o
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obj-y += clk-a20-gmac.o
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obj-y += clk-mod0.o
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obj-y += clk-sun8i-mbus.o
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obj-y += clk-sun9i-core.o
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obj-y += clk-sun9i-mmc.o
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obj-$(CONFIG_MFD_SUN6I_PRCM) += \
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clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
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clk-sun8i-apb0.o
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