6ad8838de4
Clean-up incorrect indentation, extra spaces, and missing EOF newline in schema files. Most of the clean-ups are for list indentation which should always be 2 spaces more than the preceding keyword. Found with yamllint (now integrated into the checks). Cc: linux-arm-kernel@lists.infradead.org Cc: dri-devel@lists.freedesktop.org Cc: linux-gpio@vger.kernel.org Cc: linux-i2c@vger.kernel.org Cc: linux-iio@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: alsa-devel@alsa-project.org Cc: linux-mmc@vger.kernel.org Cc: linux-mtd@lists.infradead.org Cc: linux-serial@vger.kernel.org Cc: linux-usb@vger.kernel.org Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C Acked-by: Sam Ravnborg <sam@ravnborg.org> # for display Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for-iio Signed-off-by: Rob Herring <robh@kernel.org>
98 lines
2.8 KiB
YAML
98 lines
2.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM sp804 Dual Timers
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maintainers:
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- Haojian Zhuang <haojian.zhuang@linaro.org>
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description: |+
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The Arm SP804 IP implements two independent timers, configurable for
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16 or 32 bit operation and capable of running in one-shot, periodic, or
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free-running mode. The input clock is shared, but can be gated and prescaled
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independently for each timer.
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There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
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SoCs, such as Hi1212, should use the dedicated compatible: "hisilicon,sp804".
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# Need a custom select here or 'arm,primecell' will match on lots of nodes
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select:
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properties:
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compatible:
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contains:
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oneOf:
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- const: arm,sp804
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- const: hisilicon,sp804
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- arm,sp804
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- hisilicon,sp804
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- const: arm,primecell
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interrupts:
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description: |
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If two interrupts are listed, those are the interrupts for timer
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1 and 2, respectively. If there is only a single interrupt, it is
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either a combined interrupt or the sole interrupt of one timer, as
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specified by the "arm,sp804-has-irq" property.
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minItems: 1
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maxItems: 2
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reg:
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description: The physical base address of the SP804 IP.
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maxItems: 1
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clocks:
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description: |
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Clocks driving the dual timer hardware. This list should
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be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
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clock, apb_pclk. A single clock can also be specified if the same
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clock is used for all clock inputs.
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oneOf:
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- items:
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- description: clock for timer 1
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- description: clock for timer 2
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- description: bus clock
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- items:
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- description: unified clock for both timers and the bus
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clock-names: true
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# The original binding did not specify any clock names, and there is no
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# consistent naming used in the existing DTs. The primecell binding
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# requires the "apb_pclk" name, so we need this property.
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# Use "timer0clk", "timer1clk", "apb_pclk" for new DTs.
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arm,sp804-has-irq:
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description: If only one interrupt line is connected to the interrupt
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controller, this property specifies which timer is connected to this
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line.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 2
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required:
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- compatible
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- interrupts
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- reg
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- clocks
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additionalProperties: false
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examples:
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- |
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timer0: timer@fc800000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0xfc800000 0x1000>;
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interrupts = <0 0 4>, <0 1 4>;
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clocks = <&timclk1>, <&timclk2>, <&pclk>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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