7017858eb2
This patch is used to detect the size of CPU vector registers and use riscv_v_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in a SMP system. If a core detects VLENB that is different from the boot core, then it warns and turns off V support for user space. Co-developed-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230605110724.21391-9-andy.chiu@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
37 lines
723 B
C
37 lines
723 B
C
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
/*
|
|
* Copyright (C) 2023 SiFive
|
|
* Author: Andy Chiu <andy.chiu@sifive.com>
|
|
*/
|
|
#include <linux/export.h>
|
|
|
|
#include <asm/vector.h>
|
|
#include <asm/csr.h>
|
|
#include <asm/elf.h>
|
|
#include <asm/bug.h>
|
|
|
|
unsigned long riscv_v_vsize __read_mostly;
|
|
EXPORT_SYMBOL_GPL(riscv_v_vsize);
|
|
|
|
int riscv_v_setup_vsize(void)
|
|
{
|
|
unsigned long this_vsize;
|
|
|
|
/* There are 32 vector registers with vlenb length. */
|
|
riscv_v_enable();
|
|
this_vsize = csr_read(CSR_VLENB) * 32;
|
|
riscv_v_disable();
|
|
|
|
if (!riscv_v_vsize) {
|
|
riscv_v_vsize = this_vsize;
|
|
return 0;
|
|
}
|
|
|
|
if (riscv_v_vsize != this_vsize) {
|
|
WARN(1, "RISCV_ISA_V only supports one vlenb on SMP systems");
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
return 0;
|
|
}
|