d16de9a25b
Starting in XeHP, the concept of slice has been removed in favor of DSS (Dual-Subslice) masks for various workload types. These workloads have been divided into those enabled for geometry and those enabled for compute. i915 currently maintains a single set of S/SS/EU masks for the device. The goal of this patch set is to minimize the amount of impact to prior generations while still giving the user maximum flexibility. v2: - Generalize a comment about uapi access to geometry/compute masks; the proposed uapi has changed since the comment was first written, and will show up in a future series once the userspace code is published. (Lucas) v3: - Eliminate unnecessary has_compute_dss flag. (Lucas) - Drop unwanted comment change in uapi header. (Lucas) Bspec: 33117, 33118, 20376 Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> Signed-off-by: Steve Hampson <steven.t.hampson@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210806172901.1049133-1-matthew.d.roper@intel.com
123 lines
3.2 KiB
C
123 lines
3.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_SSEU_H__
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#define __INTEL_SSEU_H__
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include "i915_gem.h"
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struct drm_i915_private;
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struct intel_gt;
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struct drm_printer;
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#define GEN_MAX_SLICES (3) /* SKL upper bound */
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#define GEN_MAX_SUBSLICES (32) /* XEHPSDV upper bound */
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#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
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#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
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#define GEN_MAX_EUS (16) /* TGL upper bound */
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#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
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#define GEN_DSS_PER_GSLICE 4
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#define GEN_DSS_PER_CSLICE 8
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#define GEN_DSS_PER_MSLICE 8
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#define GEN_MAX_GSLICES (GEN_MAX_SUBSLICES / GEN_DSS_PER_GSLICE)
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#define GEN_MAX_CSLICES (GEN_MAX_SUBSLICES / GEN_DSS_PER_CSLICE)
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struct sseu_dev_info {
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u8 slice_mask;
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u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
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u8 geometry_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
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u8 compute_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
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u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
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u16 eu_total;
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u8 eu_per_subslice;
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u8 min_eu_in_pool;
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/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
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u8 subslice_7eu[3];
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u8 has_slice_pg:1;
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u8 has_subslice_pg:1;
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u8 has_eu_pg:1;
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/* Topology fields */
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u8 max_slices;
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u8 max_subslices;
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u8 max_eus_per_subslice;
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u8 ss_stride;
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u8 eu_stride;
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};
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/*
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* Powergating configuration for a particular (context,engine).
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*/
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struct intel_sseu {
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u8 slice_mask;
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u8 subslice_mask;
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u8 min_eus_per_subslice;
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u8 max_eus_per_subslice;
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};
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static inline struct intel_sseu
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intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
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{
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struct intel_sseu value = {
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.slice_mask = sseu->slice_mask,
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.subslice_mask = sseu->subslice_mask[0],
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.min_eus_per_subslice = sseu->max_eus_per_subslice,
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.max_eus_per_subslice = sseu->max_eus_per_subslice,
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};
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return value;
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}
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static inline bool
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intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
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int subslice)
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{
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u8 mask;
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int ss_idx = subslice / BITS_PER_BYTE;
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if (slice >= sseu->max_slices ||
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subslice >= sseu->max_subslices)
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return false;
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GEM_BUG_ON(ss_idx >= sseu->ss_stride);
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mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
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return mask & BIT(subslice % BITS_PER_BYTE);
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}
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void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
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u8 max_subslices, u8 max_eus_per_subslice);
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unsigned int
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intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
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unsigned int
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intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
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u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
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void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
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u8 *subslice_mask, u32 ss_mask);
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void intel_sseu_info_init(struct intel_gt *gt);
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u32 intel_sseu_make_rpcs(struct intel_gt *gt,
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const struct intel_sseu *req_sseu);
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void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
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void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
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struct drm_printer *p);
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u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
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#endif /* __INTEL_SSEU_H__ */
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