d6c78f1ca3
riscv_v_vstate_{save,restore}() can operate only on the knowlege of
struct __riscv_v_ext_state, and struct pt_regs. Let the caller decides
which should be passed into the function. Meanwhile, the kernel-mode
Vector is going to introduce another vstate, so this also makes functions
potentially able to be reused.
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240115055929.4736-8-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
43 lines
1.0 KiB
C
43 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_RISCV_ENTRY_COMMON_H
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#define _ASM_RISCV_ENTRY_COMMON_H
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#include <asm/stacktrace.h>
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#include <asm/thread_info.h>
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#include <asm/vector.h>
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static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,
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unsigned long ti_work)
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{
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if (ti_work & _TIF_RISCV_V_DEFER_RESTORE) {
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clear_thread_flag(TIF_RISCV_V_DEFER_RESTORE);
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/*
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* We are already called with irq disabled, so go without
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* keeping track of riscv_v_flags.
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*/
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riscv_v_vstate_restore(¤t->thread.vstate, regs);
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}
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}
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#define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare
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void handle_page_fault(struct pt_regs *regs);
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void handle_break(struct pt_regs *regs);
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#ifdef CONFIG_RISCV_MISALIGNED
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int handle_misaligned_load(struct pt_regs *regs);
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int handle_misaligned_store(struct pt_regs *regs);
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#else
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static inline int handle_misaligned_load(struct pt_regs *regs)
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{
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return -1;
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}
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static inline int handle_misaligned_store(struct pt_regs *regs)
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{
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return -1;
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}
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#endif
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#endif /* _ASM_RISCV_ENTRY_COMMON_H */
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